Composite Test Generation for Multi-Core Integrated Circuits
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Solution Overview
Problem
Current methods for modeling and testing integrated circuits, especially those with multi-core processors, are overly complex and time-consuming, requiring significant computational resources and often relying on guesswork to identify relevant simulation scenarios, leading to inefficient design prototyping and characterization.
Innovation Solution
A method for generating composite tests by simulating each processor core in various states, combining simulation results to cover multiple combinations, and analyzing physical characteristics such as voltage and noise patterns, allowing for rapid evaluation of integrated circuit performance and identification of resonance conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comprehensive simulation testing is conducted for all switching scenarios in multi-core processors, then complete characterization of integrated circuit behavior is achieved, but computational time and resource consumption increase significantly
Solution Approach 1:
The patent segments the comprehensive testing problem into individual core-level simulations. Each core is tested separately with simplified switching scenarios, and the results are combined to form the complete multi-core characterization. This segmentation reduces the computational complexity from exponential (testing all multi-core combinations) to linear (testing each core independently), thereby resolving the contradiction between complete characterization and computational time.
2Measurement precision
If all possible switching scenarios are simulated to identify resonance conditions, then comprehensive noise analysis is achieved, but the complexity of test generation and execution becomes prohibitively high
Solution Approach 1:
The patent extracts and focuses on individual noise sources by isolating each core's switching activity in separate simulations. By taking out each core's contribution to the overall noise profile independently, the method simplifies test generation while maintaining comprehensive noise analysis capability. The extracted individual results are then combined to achieve complete noise characterization without the complexity of simulating all multi-core interactions simultaneously.
3Measurement precision
If invasive testing methods are used to identify logic errors in integrated circuits, then detailed behavioral understanding is achieved, but the monolithic structure prevents physical deconstruction for testing
Solution Approach 1:
The patent creates virtual copies of the integrated circuit's behavior through simulation models. Instead of physically deconstructing the monolithic device, the invention generates digital replicas that mimic the circuit's electrical and logical behavior under various switching conditions. This copying approach enables detailed behavioral understanding and invasive-style testing through software simulation, bypassing the physical inaccessibility of the actual hardware.
Data Source
AI summary
A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of Mi . . . j states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering MN*j combinations. Related apparatus, systems, techniques and articles are also described.