Composite Through Organic Vias for Semiconductor Alignment
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Solution Overview
Problem
The small size of through hole vias (THVs) in semiconductor devices makes proper alignment challenging during interconnection, leading to device defects and increased manufacturing costs, and the copper-filled THVs are prone to oxidation, reducing adhesion strength and increasing contact resistance.
Innovation Solution
The method involves forming composite through organic vias (TOVs) with varying widths in the peripheral region of semiconductor die, which includes depositing an insulating material, creating openings of different depths, and filling these with conductive material to facilitate vertical electrical interconnection, along with applying an OSP coating to reduce oxidation and improve adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper-filled through hole vias (THVs) are used for vertical electrical interconnection, then conductivity is achieved, but alignment precision deteriorates due to small size making proper alignment challenging
Solution Approach 1:
The patent changes the size parameter of the via structure by transitioning from small-diameter THVs to larger-diameter TOVs. This parameter change directly addresses the alignment precision issue while maintaining electrical interconnection functionality through the conductive material filling process.
Solution Approach 2:
The patent uses a temporary carrier structure during the via formation process that can be removed after serving its purpose. This temporary structure enables precise via formation and alignment without requiring expensive high-precision bonding equipment, effectively replacing costly equipment with a disposable process aid.
2Reliability
If copper-filled through hole vias (THVs) are used, then electrical interconnection is established, but adhesion strength decreases due to oxidation of copper
Solution Approach 1:
The patent employs a composite material structure for the via filling, using a barrier layer (such as tungsten or copper with oxidation resistance) combined with conductive material. This composite approach prevents copper oxidation while maintaining electrical conductivity, thereby preserving both adhesion strength and electrical interconnection reliability.
Solution Approach 2:
The patent creates an oxidation-resistant environment for the copper-filled vias by applying barrier layers and controlling the processing atmosphere. This inert environment protection prevents copper oxidation that would otherwise reduce adhesion strength, maintaining both electrical and mechanical performance.
3Manufacturing precision
If high-precision bonding equipment is used to achieve adequate yield, then manufacturing precision improves, but manufacturing cost increases significantly
Solution Approach 1:
The patent introduces a temporary carrier as a low-cost, disposable process element that enables precise via formation without requiring expensive high-precision bonding equipment. The carrier is removed after serving its alignment and formation purpose, effectively replacing costly equipment with an inexpensive process aid.
Solution Approach 2:
The patent performs preliminary via formation and alignment operations on the temporary carrier before final die stacking. This preliminary action establishes precise alignment and via structure in advance, eliminating the need for expensive high-precision bonding equipment during the final assembly process.
4Productivity
If smaller die size is achieved through front-end process improvements, then device density increases, but back-end interconnection complexity increases
Solution Approach 1:
The patent addresses interconnection complexity by transitioning from planar interconnection to three-dimensional vertical interconnection using through-organic vias. This dimensional change enables efficient stacking of multiple die layers, managing the increasing interconnection complexity that arises from higher device density through front-end improvements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances alignment tolerance, reduces manufacturing time, and decreases contact resistance by allowing for more precise interconnection and improved adhesion between stacked semiconductor die, thereby improving the reliability and efficiency of semiconductor device assembly.
Implementation Method 1
depositing a conductive material in the composite TOV to form a conductive TOV
Implementation Method 2
applying an OSP coating to reduce oxidation and improve adhesion
Data Source
AI summary
A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.