Composite Transistor Gate Structure to Prevent CMP Dishing
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Solution Overview
Problem
The formation of large-sized metal gates in transistors leads to dishing during chemical mechanical polishing (CMP), affecting transistor performance and increasing chip size, which is not conducive to micro-apparatus development.
Innovation Solution
A transistor structure with a gate comprising a polysilicon portion and a metal portion, where the polysilicon portion is surrounded by the metal portion, and a high dielectric constant gate dielectric structure is used, along with a capping layer, to prevent dishing during CMP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large-sized metal gate is formed, then the transistor performance is improved, but dishing occurs during CMP process affecting the gate surface quality
Solution Approach 1:
The gate is formed as a composite structure comprising a metal layer and a polysilicon layer. The metal layer provides the primary gate function and sizing, while the polysilicon layer serves as a protective cap during CMP processing. This composite structure allows the metal gate to maintain its large size for performance while the polysilicon cap prevents dishing during polishing, thus resolving the contradiction between transistor performance and gate surface quality.
2Manufacturing precision
If the metal gate size is reduced to avoid dishing, then the gate surface quality is maintained, but the chip size increases which is not conducive to micro-apparatus development
Solution Approach 1:
By using a composite metal-polysilicon gate structure, the invention maintains a large metal gate size for optimal transistor performance without incurring dishing defects. The polysilicon cap layer protects the metal gate surface during CMP while allowing the metal gate to retain its full size, thereby avoiding the need to reduce gate dimensions and preventing increase in chip area.
Solution Approach 2:
The polysilicon layer acts as an intermediary protective layer during the CMP process. It is placed over the metal gate to prevent direct contact between the CMP polishing pad and the metal gate surface, thereby preventing dishing. This intermediary layer can be selectively removed afterward, allowing the metal gate to maintain its original large size without surface defects.
3Reliability
If a replacement gate process is used to form metal gate, then the transistor performance is improved, but dishing occurs during CMP process
Solution Approach 1:
The replacement gate process is modified by forming a composite structure where a polysilicon layer is deposited over the metal layer after the metal gate is formed in the recess. This composite structure maintains the performance benefits of the metal gate while eliminating the dishing problem during subsequent CMP processes, as the polysilicon cap protects the metal gate surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively prevents dishing at the gate surface and avoids excessive reduction of threshold voltage, maintaining transistor performance while reducing chip size.
Implementation Method 1
after the CMP process, the top surface of the metal layer in the recess may produce dishing
Implementation Method 2
The gate dielectric structure includes a high dielectric constant layer
Data Source
AI summary
A transistor structure and a manufacturing method thereof are provided. The transistor structure includes a gate, doped regions and a gate dielectric structure. The gate is disposed on a substrate and includes a first portion and a second portion, wherein the second portion surrounds the first portion, and a material of the first portion is different from a material of the second portion. The doped regions are disposed in the substrate on both sides of the gate. The gate dielectric structure is disposed between the gate and the substrate.