Compound Capacitor Layout for Low Parasitic Inductance
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Solution Overview
Problem
In high-frequency applications such as 5G devices, large capacitors introduce significant parasitic inductance, leading to unwanted behavior and instability, which existing technologies fail to adequately address.
Innovation Solution
The proposed solution involves compound capacitor structures with plate-to-plate and finger-to-finger capacitors oriented in a 90-degree phase shift and anti-parallel currents to cancel inductance, optimizing capacitance and Q factor while reducing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large capacitors are used in high-frequency applications, then capacitance is increased, but parasitic inductance increases leading to instability
Solution Approach 1:
The capacitor structure is divided into multiple individual capacitors arranged in parallel, where each capacitor has its own plates and interconnects. This segmentation allows the parasitic inductance of each individual capacitor to be minimized independently, and when connected in parallel, the total capacitance increases while the overall parasitic inductance remains low due to the distributed nature of the interconnects.
Solution Approach 2:
The patent utilizes three-dimensional stacking of capacitor plates across multiple metal layers (e.g., M1, M2, M3, M4) to increase capacitance in the vertical dimension rather than expanding horizontally. This multi-layer plate-to-plate and finger-to-finger configuration allows large total capacitance to be achieved within a small footprint while maintaining short interconnect lengths that minimize parasitic inductance.
2Quantity of substance
If capacitor size is increased to achieve higher capacitance, then capacitance is improved, but parasitic inductance increases
Solution Approach 1:
Multiple capacitors are merged in parallel connection to achieve high total capacitance. The parallel configuration allows the capacitances to add up (C_total = C1 + C2 + ... + Cn) while the parasitic inductances, being in parallel, combine in a way that reduces the overall equivalent inductance, thus achieving high capacitance without proportionally increasing parasitic inductance.
Solution Approach 2:
The patent employs multi-layer metal structures (M1-M4) with plates extending vertically across layers, creating plate-to-plate and finger-to-finger capacitors in three dimensions. This vertical stacking increases capacitance density without increasing the horizontal footprint, and the short via connections between layers minimize the parasitic inductance path length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a high Q factor and resonance frequency, reducing loss and ensuring sufficient quality for high-frequency applications like 5G devices by effectively canceling inductance and increasing capacitance.
Implementation Method 1
plate-to-plate and finger-to-finger capacitors oriented in a 90-degree phase shift and anti-parallel currents to cancel inductance
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
Capacitors are disclosed. A capacitor includes a plate-to-plate capacitor and a finger-to-finger capacitor. The plate-to-plate capacitor includes at least a first plate and a second plate. The second plate is in proximity to the first plate. The finger to finger capacitor is in proximity to the first plate. The finger to finger capacitor includes a first plurality of finger elements and a second plurality of finger elements. The second plurality of finger elements is interleaved with the first plurality of finger elements. The first plurality of finger elements is electrically connected to the first plate and the second plurality of finger elements is electrically connected to the second plate. The second plurality of finger elements and the first plate form additional plate-to-plate capacitors.