Compound Semiconductor FET Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor devices face increased parasitic capacitance as the distance between the gate electrode and the source and drain electrodes is reduced, hindering the enhancement of high-frequency characteristics in terahertz integrated circuits.
Innovation Solution
The semiconductor device features a field-effect transistor with at least one of the source or drain electrodes formed on the side of the substrate, reducing the distance between the gate electrode and the source and drain electrodes, thereby minimizing parasitic capacitance and improving high-frequency characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the distance between the gate electrode and the source and drain electrodes is reduced to speed up transistors, then the high-frequency characteristics are improved, but the parasitic capacitance between the gate electrode and the source and drain electrodes increases
Solution Approach 1:
The invention transitions from a planar configuration to a three-dimensional stacked configuration. The gate electrode and source/drain electrodes are arranged on different surfaces of the semiconductor substrate, utilizing the vertical dimension to reduce parasitic capacitance while maintaining short electrical distance. This dimensional change allows the electrodes to be physically close for low capacitance but electrically isolated through the substrate thickness.
Solution Approach 2:
The gate electrode and source/drain electrodes are nested within the semiconductor substrate structure, with each electrode type positioned on opposite surfaces. This nesting arrangement allows the electrodes to be embedded within the substrate volume, reducing the parasitic capacitance that would exist if they were placed on the same surface, while maintaining the short distance needed for high-speed operation.
2Ease of manufacture
If the gate electrode and the source and drain electrodes are formed on the same surface to simplify fabrication, then the manufacturing process is easier, but the parasitic capacitance increases and transistor speed decreases
Solution Approach 1:
The invention resolves the fabrication complexity by utilizing the vertical dimension of the substrate. Instead of requiring complex lateral patterning to separate electrodes on the same surface, the gate and source/drain electrodes are formed on opposite surfaces through straightforward vertical stacking, maintaining ease of manufacture while achieving the speed performance.
Data Source
AI summary
A field-effect transistor includes a channel layer made of a compound semiconductor and formed on a substrate; a gate electrode formed on the channel layer; and a source electrode and a drain electrode, which are formed with the gate electrode interposed therebetween. At least one of the source electrode and the drain electrode is formed on a substrate side of the channel layer.