Compound Instructions in Multi-Threaded Processors
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Solution Overview
Problem
Multi-threaded processors face inefficiencies due to high silicon area and cost requirements for increasing the number of ports in register storage, which hinder fast thread switching and processor utilization, especially when executing complex instructions like 'ADD' that require multiple read and write ports.
Innovation Solution
A small, shared internal register store with additional read/write ports is introduced, allowing compound instructions to utilize these extra resources without duplicating them for each thread, and a 'no-reschedule' bit prevents thread switching during execution of these instructions, optimizing processor utilization without increasing the main register store's port count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of ports in the main register store is increased to enable fast thread switching and execute complex instructions, then processor performance and thread switching speed are improved, but silicon area and device cost increase significantly
Solution Approach 1:
The patent divides the register store into two segments: a main register store with limited ports for general use, and a smaller internal register store with additional ports specifically for compound instructions. This segmentation allows the system to have high-performance access paths without duplicating the entire register store for each thread, thus improving processor performance while controlling silicon area.
Solution Approach 2:
The patent adds another dimension to the register access hierarchy by introducing internal registers that are closely coupled with the execution unit. This creates a multi-level register architecture where the internal register store provides fast access for critical operations without requiring proportional increases in the main register store's port count, effectively adding performance capability without linearly increasing area.
2Loss of time
If the number of ports in the main register store is increased to enable fast thread switching and execute complex instructions, then thread switching speed is improved, but device cost increases
Solution Approach 1:
The patent segments the thread switching function between the main register store (for general thread state storage) and the internal register store (for active thread execution). This allows thread switching to utilize the internal registers' additional ports without requiring the main register store to have proportionally more ports, reducing device cost while maintaining fast switching capability.
Solution Approach 2:
The internal register store acts as an intermediary between the main register store and the execution unit. It provides a buffer that facilitates fast thread switching and complex instruction execution without requiring direct high-port-count access to the main register store, thereby reducing the overall device cost while maintaining performance.
3Area of stationary object
If a single internal register store is shared by all threads instead of duplicating it, then silicon area is reduced, but thread switching capability is constrained
Solution Approach 1:
The patent implements dynamic thread switching control where the processor prevents switching to another thread while internal registers are being used by the current thread. This dynamic control mechanism allows a single shared internal register store to serve multiple threads effectively, reducing silicon area while maintaining thread switching capability through proper resource management.
Solution Approach 2:
The internal register store is designed as a universal resource that can be used by any executing thread, rather than being dedicated to specific threads. This multi-functional design reduces the total number of registers needed while the compiler-generated compound instructions ensure that threads using internal registers complete their operations without interruption, maintaining productivity.
Data Source
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AI summary
A multi threaded processor for executing a plurality of threads in dependence on the availability of resources that each thread requires for it to execute is disclosed. The processor comprises means for determining which thread should execute; means for switching between execution of threads in dependence on the result of the determination, each thread being coupled to a respective register means for storing the state of the thread and for use in executing instructions on the thread; further register means shared by all the threads, wherein executing threads use the further register means to improve execution performance; and means for preventing switching of execution to another thread while the internal register means is in use.