Compound Logic Flip-Flop for Lower Propagation Delay
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Solution Overview
Problem
Existing digital circuits face delays in propagating results of combinational logic operations to flip-flops due to the need for separate stages and additional logic gates, which can slow down circuit operation.
Innovation Solution
A compound logic flip-flop is introduced, featuring multiple input stages that perform logic functions during a first phase of a clock cycle and store results, which are then logically combined by an output stage during a second phase, eliminating the need for separate combinational logic circuits and reducing propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate combinational logic circuits are used to perform logic functions before flip-flops, then the logic operations can be performed, but propagation delays increase and circuit operation slows down
Solution Approach 1:
The patent merges the combinational logic functions directly into the flip-flop structure by adding input stages to the conventional master-slave flip-flop. The logic gates (AND, OR, NAND, NOR) are integrated within the flip-flop circuit itself, allowing logic operations and data latching to occur in a unified structure rather than as separate sequential stages. This integration eliminates the propagation delay between separate logic circuits and flip-flops.
2Adaptability or versatility
If multiple separate stages are used to perform logic functions and store results, then logic operations can be completed, but the circuit complexity increases
Solution Approach 1:
The patent creates a universal flip-flop structure that can perform multiple logic functions (AND, OR, NAND, NOR) within a single integrated circuit. By incorporating select lines and configurable logic gates in the input stages, the same flip-flop device can be programmed to perform different logic operations depending on the select signal configuration, eliminating the need for multiple specialized circuits.
Data Source
AI summary
A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function.