Compound MOS Capacitor for PLL Jitter Reduction

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Solution Overview

Problem

Conventional phase-locked loops face issues with current leakage in MOS capacitors, requiring multiple voltage sources and compromising jitter performance due to asymmetric charging/discharging periods and signal disturbances between high-voltage and low-voltage devices.

Innovation Solution

The implementation of compound MOS capacitors, comprising a HV PMOS and HV NMOS capacitor, both powered by a low bias voltage source, with connected gates receiving a control signal to maintain constant capacitance and reduce voltage source requirements, thereby improving jitter performance and expanding the operational range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thick oxide is used at the gate of MOS capacitors to prevent current leakage, then current leakage is reduced, but the charging/discharging periods become asymmetric and the operational voltage range is limited

Engineering Contradiction:
Improvecurrent leakage preventionVSAvoidoperational voltage range
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent combines a first MOS capacitor with thick gate oxide and a second MOS capacitor with thin gate oxide into a compound MOS capacitor structure. The thick oxide capacitor provides low leakage current, while the thin oxide capacitor enables broader voltage operation range, achieving both reliability and operational flexibility simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Different regions of the compound MOS capacitor have different oxide thicknesses tailored to specific functions: the thick oxide region handles voltage blocking and leakage prevention, while the thin oxide region provides capacitance over a wider voltage range. Each part has optimized local properties for its specific role.

Inventive Principle:
Principle #3Local quality

2Reliability

If separate high-voltage and low-voltage sources are used to power HV and LV devices, then current leakage is prevented, but the device complexity and number of voltage sources increase

Engineering Contradiction:
Improvecurrent leakage preventionVSAvoidnumber of voltage sources
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The compound MOS capacitor merges HV and LV device functionalities into a single integrated structure that can be powered by a single low-voltage source. The thick oxide portion handles high-voltage stress while the thin oxide portion operates at low voltage, eliminating the need for separate HV/LV power supplies.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The compound MOS capacitor serves multiple functions: it provides voltage blocking capability like an HV device, maintains low leakage current, and enables constant capacitance operation across a wide voltage range, all while being compatible with a single low-voltage power source like an LV device.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If conventional HV MOS capacitors are used in the loop filter, then current leakage is reduced, but the jitter performance deteriorates due to signal disturbances between different voltage sources

Engineering Contradiction:
Improvecurrent leakage preventionVSAvoidjitter performance
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

By merging HV and LV functionalities into a single compound MOS capacitor, the patent eliminates the interface between separate HV and LV circuits that causes signal disturbances and jitter. The unified structure operates from a single voltage source, removing the source of timing disturbances.

Inventive Principle:
Principle #5Merging (Combining)

4Stability of the object's composition

If the gate voltage of HV MOS capacitors is limited to a narrow range to maintain constant capacitance, then capacitance stability is achieved, but the operational flexibility and voltage range are reduced

Engineering Contradiction:
Improvecapacitance stabilityVSAvoidoperational voltage range
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The compound MOS capacitor combines two capacitors with different oxide thicknesses where the thick oxide capacitor maintains stable capacitance at high voltages while the thin oxide capacitor provides operational flexibility across a broader voltage range, achieving both stability and adaptability simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces current leakage, minimizes the number of voltage sources needed, and enhances jitter performance by maintaining a constant capacitance and reducing signal disturbances, allowing for high-frequency oscillations with improved operational range and reduced current consumption.

Implementation Method 1

The capacitance of the compound MOS capacitor is near a constant value. The gate of the compound MOS capacitor has a wider normal operation range than the gates of the conventional HV MOS capacitors.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

the current leakage damages the function of MOS capacitors a lot. To deal with the current leakage, the MOS capacitors of phase-locked loop are designed to have thick oxide at the gates.

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS7609108B2Phase-locked loop and compound MOS capacitor thereof
Publication Date: 2009.10.27 VIA TECH INC
  • US7609108B2 patent drawing
  • US7609108B2 patent drawing
  • US7609108B2 patent drawing

AI summary

Compound MOS capacitors and phase-locked loop with the compound MOS capacitors are disclosed. In the phase-locked loop, the compound MOS capacitors of the loop filter are HV (high voltage) devices, and the voltage control oscillator is a LV (low voltage) device. The compound MOS capacitor comprises a HV PMOS capacitor having a base coupled to a source terminal of a low voltage source and a HV NMOS capacitor having a base coupled to a ground terminal of the low voltage source. The gates of the HV PMOS capacitor and the HV NMOS capacitor are connected together to receive a control voltage. The capacitance of the compound MOS capacitor is near constant in any control voltage.