Compound PLL Clock Recovery for Noisy Bursty Signals
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Solution Overview
Problem
Clock recovery in noisy bursty channels is challenging due to extraneous transitions caused by noise, making direct symbol-by-symbol recovery unreliable, and existing oscillators face issues with precision, tuning range, and phase noise, especially during signal gaps and when burst frequencies are not correlated.
Innovation Solution
A clock recovery circuit with an outer main tracking PLL, a digital loop filter, and an analog/digital hybrid NCO, which includes an inner loop PLL operating as a fractional N synthesizer, maintains accurate timing by freezing the clock frequency between bursts and using a burst detector to minimize phase creep and random walk, while the inner loop limits noise addition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a controlled oscillator is used to maintain fixed frequency and phase between bursts, then clock stability is improved, but the oscillator cannot provide wide tuning range and wide modulation bandwidth needed for acquisition and tracking during bursts
Solution Approach 1:
The patent applies dynamics by making the oscillator characteristics changeable over time. The system dynamically switches between two operational modes: during signal bursts, the oscillator provides wide tuning range and modulation bandwidth for rapid acquisition and tracking; during gaps between bursts, the oscillator maintains fixed frequency and phase for stability. This temporal dynamic behavior resolves the contradiction between stability and adaptability.
Solution Approach 2:
The patent changes the operational parameters of the oscillator based on signal presence. When a signal burst is detected, the system enables wide bandwidth and tuning range parameters for acquisition and tracking. When no signal is present, the system switches to a stable, fixed-frequency mode. This parameter switching allows the system to optimize performance for each operational condition, resolving the contradiction between stability and versatility.
2Speed
If the PLL control system bandwidth is widened to allow rapid response during bursts, then acquisition speed is improved, but phase noise degradation occurs due to noise sources in the PLL
Solution Approach 1:
The patent applies periodic action by operating the PLL at different bandwidth settings during different time periods. During signal bursts, the PLL operates with wide bandwidth to enable rapid acquisition and tracking. During gaps between bursts, the PLL switches to narrow bandwidth or is disabled to prevent phase noise degradation. This periodic switching of operational modes allows the system to achieve fast acquisition when needed while minimizing phase noise when the signal is absent.
Solution Approach 2:
The system dynamically adjusts the PLL control system bandwidth based on signal presence. When a burst is detected, the bandwidth is widened to allow rapid response and tracking. When no signal is present, the bandwidth is narrowed or the PLL is disabled to prevent noise amplification. This dynamic bandwidth adjustment resolves the contradiction between acquisition speed and phase noise performance.
3Device complexity
If direct symbol-by-symbol recovery is used in noisy channels, then clock recovery simplicity is improved, but reliability deteriorates due to extraneous transitions caused by noise
Solution Approach 1:
The patent introduces an intermediary mechanism - a phase-locked loop with burst detection - between the noisy received signal and the clock recovery process. The burst detector identifies valid signal bursts, and the PLL processes only these validated bursts to generate clock timing. This intermediary filtering mechanism blocks extraneous transitions caused by noise while preserving valid signal transitions, thereby improving reliability without significantly increasing system complexity.
Data Source
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AI summary
A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is "frozen" to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal.