Compound Semiconductor ESD Protection Devices for RF Linearity
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Solution Overview
Problem
Compound semiconductor ESD protection devices, particularly those using series-connected diodes, introduce nonlinearity during RF operations, leading to harmonic distortions and intermodulation distortion due to voltage-dependent capacitance across the gate and source/drain, which is not effectively addressed by conventional designs.
Innovation Solution
The use of plural compound semiconductor E-FETs or multi-gate E-FETs with gate capacitors connected in parallel to the parasitic capacitance, reducing RF bias voltage and nonlinearity by AC-connecting at least one gate to the source, drain, or inter-gate region, thereby improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits using series-connected diodes are used, then ESD protection function is achieved, but nonlinearity and harmonic distortions occur during RF operation
Solution Approach 1:
The patent changes the operating parameters of the E-FET by applying a negative DC bias voltage to the gate, shifting the operation point away from the sub-threshold region where voltage-dependent capacitance causes nonlinearity. This parameter change maintains ESD protection while reducing harmonic distortions during RF operation
Solution Approach 2:
The patent introduces a capacitor as an intermediary element connected between the gate and source/drain. This capacitor acts as a bypass for RF signals, preventing them from developing across the voltage-dependent parasitic capacitance and thereby reducing nonlinearity while maintaining the ESD protection function
2Area of stationary object
If ESD protection circuits are integrated on the same chip, then IC module size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent uses the same compound semiconductor material system and fabrication processes for both the main RF circuit elements and the ESD protection devices. This universal approach allows both functional blocks to be integrated on the same chip using identical manufacturing steps, reducing overall complexity despite the added functionality
Solution Approach 2:
The patent combines the ESD protection circuit with the main RF circuit on the same chip, merging previously separate functions into a single integrated device. This consolidation reduces the overall IC module size while the use of common fabrication processes keeps manufacturing complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces RF signal nonlinearity and harmonic distortions, enhancing the performance of ESD protection devices by integrating ESD protection circuits on the same chip, reducing IC module size, and simplifying manufacturing processes.
Implementation Method 1
The gate capacitor is in parallel with the gate capacitance (denoted by Cgs) of the E-FET. The inclusion of the gate capacitor reduces the RF bias voltage across the Cgs and the nonlinearity of the signal produced by Cgs
Data Source
AI summary
The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resistor, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.