Compound Semiconductor Layout Using Localized Dielectric Blocks
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Solution Overview
Problem
Conventional polyimide isolation layers in compound semiconductor integrated circuits are not efficiently removable from areas where they are not needed, leading to reduced moisture resistance and impedance issues due to their water absorption and dielectric properties.
Innovation Solution
A layout method that defines specific dielectric areas for forming low dielectric blocks within compound semiconductor integrated circuits, allowing for the efficient removal of unnecessary isolation layers and optimizing the thickness, area, and shape of these blocks to enhance moisture resistance and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polyimide isolation layer is formed on the bottom metal layer to isolate cross-connection, then the isolation between two metal layers having different potentials is improved, but the moisture resistance ability of the compound semiconductor integrated circuit is reduced due to water absorption
Solution Approach 1:
The patent applies local quality by forming the polyimide isolation layer only in specific areas where isolation is needed (intersection area and adjacent area of cross-connection) rather than uniformly across the entire bottom metal layer. This localized approach maintains the necessary electrical isolation while minimizing the total area of water-absorbing material, thereby preserving moisture resistance ability.
Solution Approach 2:
The isolation layer is segmented to exist only in the intersection area and adjacent area where cross-connection isolation is required, rather than covering the entire metal layer. This segmentation eliminates unnecessary polyimide material from areas where isolation is not needed, reducing overall water absorption while maintaining functional isolation where required.
2Reliability
If the polyimide isolation layer is formed in the intersection area to isolate metal layers, then the isolation function is achieved, but the impedance of the compound semiconductor integrated circuit is affected due to the dielectric properties of polyimide
Solution Approach 1:
The patent applies local quality by restricting the polyimide isolation layer to only the intersection area and adjacent area where isolation is functionally required. By limiting the isolation layer to this specific local region rather than extending it broadly, the patent minimizes the total dielectric material present in the circuit path, thereby reducing the overall impedance impact while maintaining the necessary isolation function at the cross-connection point.
3Reliability
If the polyimide isolation layer is used for isolating metal layers, then the isolation requirement is satisfied, but the moisture resistance ability is significantly reduced due to the wide area coverage
Solution Approach 1:
The patent applies local quality by forming the polyimide isolation layer only in the intersection area and adjacent area of the cross-connection, rather than covering the entire bottom metal layer. This localized formation strategy ensures that the isolation function is provided exactly where needed while minimizing the total quantity of polyimide material present in the structure, thereby reducing overall water absorption.
Solution Approach 2:
The isolation layer is segmented to exist only in the specific intersection area and adjacent area where cross-connection isolation is required, rather than covering the entire metal layer. This segmentation eliminates unnecessary polyimide material from areas where isolation is not needed, directly reducing the total quantity of water-absorbing substance in the integrated circuit.
Data Source
AI summary
A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.