Compressing Cache Coherent Addresses to Reduce Silicon Area
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Solution Overview
Problem
Modern computer systems with heterogeneous processing units face inefficiencies due to the need to store, transmit, and operate on full memory addresses, which consume significant silicon area, increase power consumption, and limit clock speed.
Innovation Solution
A method and system for compressing addresses in cache coherent memory locations, using fewer bits to represent memory regions, thereby reducing silicon area usage, power consumption, and increasing clock speed, while allowing for lower manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full addresses are stored and transmitted in cache coherent subsystems, then address accuracy and completeness are maintained, but silicon area increases significantly
Solution Approach 1:
The address space is segmented into two parts: a coherent subsystem with compressed addresses and a non-coherent subsystem with full addresses. The compression logic divides the full address into a compressed portion for internal use and a decompressed portion for external interfaces, effectively segmenting the address representation based on functional requirements.
Solution Approach 2:
Different address representations are used in different locations within the system. Compressed addresses are used locally within the cache coherent subsystem to minimize area, while full addresses are used at non-coherent interfaces where complete address information is required. This local differentiation optimizes area without sacrificing external compatibility.
2Loss of information
If full addresses are transmitted through the transport mechanism, then address completeness is maintained, but power consumption increases
Solution Approach 1:
The address transmission is segmented into compressed form for internal coherent subsystem communication and full form for external non-coherent communication. This segmentation allows the system to minimize power consumption during internal operations while maintaining address completeness when required by external interfaces.
Solution Approach 2:
The system uses partial address information (compressed form) for internal operations where full address detail is unnecessary, reducing power consumption. Full addresses are transmitted only when excessive information is required by external non-coherent subsystems, optimizing the balance between power consumption and information completeness.
3Measurement precision
If full addresses are operated on by processing units, then address operation accuracy is maintained, but logic gate delay increases
Solution Approach 1:
Address operations are segmented into compressed form for internal coherent subsystem operations and full form for external operations. The compression logic divides the address processing path, allowing faster operations on compressed addresses within the coherent subsystem while maintaining accuracy for external interfaces.
Solution Approach 2:
Different address processing qualities are applied locally: compressed addresses are used for internal operations where speed is critical, while full addresses are used at interfaces where operational accuracy with external systems is required. This local differentiation enables higher clock speeds without sacrificing external compatibility.
4Adaptability or versatility
If more address bits are used to access all legally addressable memory locations, then address coverage is complete, but device complexity increases
Solution Approach 1:
The address handling is segmented into compressed representation for internal coherent subsystem and full representation for external interfaces. This segmentation allows the system to achieve complete address coverage when needed while reducing device complexity during internal operations where full address space is not required.
Solution Approach 2:
The address representation is dynamic rather than static. The system automatically switches between compressed and full address representations based on the operational context, allowing adaptability to different address coverage requirements while minimizing device complexity in the most common internal operations scenario.
Data Source
AI summary
Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and operating upon unnecessary address information. Compression is performed according to any appropriate lossless algorithm, such as discarding of bits or code book lookup. The algorithm may be chosen according to constraints on logic delay and silicon area. An algorithm for minimum area would use a number of bits equal to the rounded up binary logarithm of the sum of all addresses of all memory regions. A configuration tool generates a logic description of the compression algorithm. The algorithm may be chosen automatically by the configuration tool. Decompression may be performed on addresses exiting the coherent subsystem.