Compressed Access Map Storage for Accurate Cache Prefetching
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Solution Overview
Problem
Existing prefetching techniques in processors face challenges in accurately predicting memory access patterns, leading to inefficiencies in cache usage, increased power consumption, and circuit area utilization, while also failing to adapt to different workload types and metadata access patterns.
Innovation Solution
Implementing a Bayesian pattern engine (BPE) for program counter-based learning, compressed map storage for demoted entries, adaptive prefetch constraint adjustment, fuzzy pattern matching, and prefetching for security tag metadata to enhance prefetch accuracy and efficiency across multiple cache levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prefetching is implemented to reduce memory latency, then processor performance is improved, but power consumption and circuit area increase
Solution Approach 1:
The patent implements selective prefetching where only certain cache blocks are prefetched based on access pattern analysis rather than prefetching all blocks. The system performs partial prefetching actions - launching prefetches only when confidence thresholds are met, and using compressed representations for demoted entries to reduce the overhead. This balances performance improvement with reduced power consumption compared to aggressive prefetching schemes.
2Productivity
If prefetching is implemented to reduce memory latency, then processor performance is improved, but circuit area increases
Solution Approach 1:
The patent extracts and separates the access pattern analysis function into a dedicated pattern recognition unit that operates independently from the main prefetch logic. Demoted entries are moved to a separate compressed storage structure. This extraction allows the main prefetch circuit to remain compact while still providing advanced prefetching capabilities through the separate analysis unit.
Solution Approach 2:
The patent changes the representation parameters of demoted prefetch entries by using compressed formats with fewer bits per entry. Instead of storing full access pattern details, the system uses simplified representations that capture essential patterns while occupying less circuit area. This parameter change enables maintaining performance benefits with reduced hardware footprint.
3Loss of time
If aggressive prefetching is performed to improve cache hit rate, then memory latency is reduced, but cache eviction of useful data occurs
Solution Approach 1:
The patent implements feedback mechanisms where the system monitors actual access patterns and compares them with predicted patterns. The pattern recognition unit continuously learns from observed accesses and adjusts prefetch decisions accordingly. When predictions are validated by actual accesses, the system maintains aggressive prefetching; when predictions fail, the system reduces prefetching intensity. This feedback loop ensures cache hits are improved without causing excessive eviction of useful data.
4Productivity
If prefetching is implemented to reduce memory latency, then processor performance is improved, but prefetch accuracy decreases leading to ineffective prefetching
Solution Approach 1:
The patent performs preliminary analysis of access patterns before launching prefetch operations. The pattern recognition unit examines historical access data and identifies patterns with sufficient confidence before initiating prefetches. This preliminary action filters out low-confidence predictions, ensuring that only accurate prefetches are launched. The system prepares and validates patterns in advance, improving prefetch accuracy while maintaining performance benefits.
Data Source
AI summary
Disclosed techniques related to compressed storage for access maps demoted from a prefetch table. In some embodiments, prefetch circuitry stores access map data based on address information corresponding to memory accesses, where a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region. The prefetch circuit may generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache. Compressed map storage circuitry may store first data from a first access map, where the first data is a proper subset of data stored in the first access map prior to demotion of the first access map from the prefetch table. At least a portion of the first data may be a compressed version of data from the first access map.