Compressed Data Address Mapping for Memory I/O and Garbage Collection
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Solution Overview
Problem
Existing memory systems face challenges in maintaining efficient I/O performance when data compression is implemented due to increased size and cache miss rates of the logical-to-physical address conversion table, and inefficient garbage collection processes.
Innovation Solution
The memory system maintains an address mapping table that includes offset and size information for compressed data in the physical cluster headers, periodically updates the average compression ratio to optimize garbage collection, and invalidates redundant entries in the user log to prevent erroneous data determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data compression is implemented in memory systems, then storage capacity is improved, but the size of the logical-to-physical address conversion table increases and cache hit ratio deteriorates
Solution Approach 1:
The patent segments the address conversion table into multiple tables, each managing a specific range of logical addresses. This segmentation reduces the size of individual tables that need to be cached, thereby improving cache hit ratios while maintaining comprehensive address mapping capabilities for compressed data
Solution Approach 2:
The patent introduces a new dimension to address management by storing not only physical addresses but also offset information and compression ratios in the address conversion table. This additional dimensional information enables efficient retrieval of compressed data without requiring the entire compressed data structure to be cached
2Quantity of substance
If data compression is implemented in memory systems, then storage capacity is improved, but I/O performance deteriorates
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and storing offset information and compression ratios in the address conversion table during the data writing phase. This preliminary preparation enables rapid data retrieval during read operations, as the system can directly compute the location and size of compressed data without performing complex calculations at retrieval time
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of offset information stored in the address conversion table. This intermediary enables direct navigation to compressed data locations, acting as a bridge between logical addresses and physical compressed data positions, thereby improving I/O performance without sacrificing storage capacity
3Speed
If compression information is stored in address conversion table, then data retrieval is improved, but table size increases
Solution Approach 1:
The patent extracts only the essential compression information (offset and compression ratio) needed for data retrieval and stores it in the address conversion table, rather than storing complete compression metadata. This selective extraction provides sufficient information for fast data retrieval while minimizing the increase in table size
Data Source
AI summary
A memory system includes a nonvolatile memory and a controller. The controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. The controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. The second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.