Compressed Bitcell ROM for Area and Power Reduction
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Solution Overview
Problem
Existing read-only memory (ROM) designs face challenges in reducing design footprint and power consumption while maintaining yield and access time.
Innovation Solution
The proposed solution involves a unique column mux select technique and data compression along a read-wordline (RWL), allowing for more efficient storage of multiple bits in a single bitcell, which reduces macro area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional ROM designs are used, then data storage capacity is maintained, but design footprint area is larger and power consumption is higher
Solution Approach 1:
The patent implements data compression by nesting multiple bit values within a single bitcell structure. The compressed bitcell encodes multiple bits of information using shared transistors and storage nodes, effectively placing one bitcell inside another functional hierarchy to achieve higher density without proportionally increasing physical area
Solution Approach 2:
The patent merges multiple bitcell functions into a single compressed bitcell unit. By combining shared transistors (e.g., access transistors, pull-down transistors) and storage nodes across multiple logical bitcells, the design achieves area reduction while maintaining the ability to store and retrieve multiple bit values through selective decoding
2Area of stationary object
If miniaturization is increased to reduce area, then design footprint is reduced, but yield maintenance requires additional layout mandates that prevent proportional area reduction
Solution Approach 1:
The compressed bitcell structure serves multiple functions simultaneously: it stores multiple bit values, provides selective access through column decoders, maintains yield through robust shared transistor design, and reduces area by eliminating redundant circuitry. This multi-functionality allows the design to achieve miniaturization without sacrificing reliability
3Use of energy by moving object
If traditional bitcell structures are used, then data access is straightforward, but power consumption (both dynamic and static) is higher
Solution Approach 1:
The patent segments the data access process into distinct phases: column selection through decoders, row selection through wordlines, and sensing through shared bitlines. This segmentation allows power to be consumed only during active access operations rather than continuously, reducing static power while maintaining ease of operation through structured control signals
Data Source
AI summary
The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline through the drain of the transistor for local bitline sensing. Various other methods, systems, and computer-readable media are also disclosed.