Compressed Branch Target Buffer for Microprocessor Prediction

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Solution Overview

Problem

Branch instructions in microprocessors cause delays due to the time difference between fetching and evaluating branch instructions, leading to inefficiencies in instruction fetch throughput, which existing branch prediction techniques struggle to fully mitigate.

Innovation Solution

Incorporating both an uncompressed and a compressed branch target buffer within the branch prediction unit, allowing for efficient storage and prediction of up to two branch instructions per cycle by optimizing space usage and attribute compression, thereby reducing waste and improving prediction accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If an uncompressed branch target buffer is used to store data for multiple branch instructions, then prediction capacity is improved, but space wastage increases when fewer branches need to be stored

Engineering Contradiction:
Improveprediction capacityVSAvoidspace wastage
Core Design Contradiction:
Adaptability or versatilityVSLoss of substance

Solution Approach 1:

The branch target buffer is segmented into multiple ways (sets), with each way containing entries that can be independently selected. This allows the buffer to adaptively store data for different numbers of branch instructions (1, 2, or more) by activating only the necessary ways, thereby reducing space wastage while maintaining prediction capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer structure dynamically adapts to the actual number of branch instructions by selectively enabling or disabling ways based on current needs. The system can transition between storing data for one branch, two branches, or more branches by controlling which ways are active, making the buffer size flexible rather than fixed.

Inventive Principle:
Principle #15Dynamics

2Productivity

If the branch target buffer entries store data for up to two branch instructions, then support for multiple branches per cycle is improved, but complexity of buffer management increases

Engineering Contradiction:
Improvebranches per cycleVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer entries are segmented into multiple ways, where each way can independently store data for branch instructions. This segmentation allows the system to support up to two branches per cycle by activating two ways, while simplifying management by treating each way as an independent storage unit with uniform structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different ways within the buffer can have different characteristics or be configured for specific purposes. This allows optimized management where each way can be independently controlled and managed, reducing overall complexity by localizing management tasks to individual ways rather than managing the entire buffer as a single complex unit.

Inventive Principle:
Principle #3Local quality

3Productivity

If branch prediction techniques are enhanced to reduce delays, then instruction fetch throughput is improved, but the complexity of prediction logic increases

Engineering Contradiction:
Improveinstruction fetch throughputVSAvoidprediction logic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The prediction logic is segmented into multiple ways in the branch target buffer, allowing parallel evaluation of multiple branch predictions. This segmentation enables enhanced throughput by processing multiple branches simultaneously while keeping each individual prediction logic unit relatively simple and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple simple prediction logic units (ways) are merged into a single buffer structure that operates together to provide enhanced prediction capability. By combining multiple simple units rather than creating one complex prediction logic, the system achieves high throughput while maintaining manageable complexity at the component level.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3507688B1Branch target buffer compression
Publication Date: 2021.07.14 ADVANCED MICRO DEVICES INC
  • EP3507688B1 patent drawingFigure 1
  • EP3507688B1 patent drawingFigure 2
  • EP3507688B1 patent drawingFigure 3

AI summary

Techniques for improving branch target buffer ("BTB") operation. A compressed BTB is included within a branch prediction unit along with an uncompressed BTB. To support prediction of up to two branch instructions per cycle, the uncompressed BTB includes entries that each store data for up to two branch predictions. The compressed BTB includes entries that store data for only a single branch instruction for situations where storing that single branch instruction in the uncompressed BTB would waste space in that buffer. Space would be wasted in the uncompressed BTB due to the fact that, in order to support two branch lookups per cycle, prediction data for two branches must have certain features in common (such as cache line address) in order to be stored together in a single entry.