Compressed Cache Decompression on Page Fault Latency
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Solution Overview
Problem
Current compressed cache technologies face latency issues during page faults due to serialized operations, limiting the aggressiveness of page swapping and memory utilization in computing systems, which can lead to performance penalties and increased costs.
Innovation Solution
Implementing a hardware decompression accelerator and parallel decompression techniques to overlap decompression operations with other processing steps, allowing for more aggressive swapping to a compressed cache and reducing latency by 28%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If compressed cache technologies are used to increase memory utilization, then memory capacity is improved, but page fault processing latency increases due to serialized operations
Solution Approach 1:
The patent segments the decompression operation into independent parallel tasks by dividing the compressed page into multiple chunks and assigning them to different processing cores. This segmentation allows simultaneous decompression of multiple chunks across available CPU cores, transforming the previously serialized operation into a parallel process that reduces overall latency while maintaining high memory utilization.
Solution Approach 2:
The patent implements preliminary action by pre-calculating chunk boundaries and preparing decompression descriptors before actual page fault handling. The work descriptor is pre-configured with source and destination addresses, chunk sizes, and core assignments, allowing immediate parallel execution upon page fault detection without sequential processing delays.
2Quantity of substance
If page swapping is made more aggressive to improve memory utilization, then memory capacity is improved, but performance penalties increase due to latency
Solution Approach 1:
By segmenting the decompression workload into independent chunks that can be processed in parallel across multiple cores, the system can handle more page swaps simultaneously without performance degradation. This enables more aggressive swapping strategies while maintaining high productivity through concurrent processing of multiple swap operations.
Solution Approach 2:
The patent ensures continuity of useful action by keeping all CPU cores actively engaged in decompression work whenever page faults occur. Instead of idle cycles waiting for sequential decompression to complete, the system continuously utilizes available computational resources to process decompression chunks in parallel, eliminating performance penalties associated with aggressive swapping.
3Device complexity
If serialized decompression operations are used to simplify processing, then device complexity is reduced, but page fault processing latency increases
Solution Approach 1:
The patent applies segmentation by dividing the compressed page into manageable chunks with pre-calculated boundaries. This segmentation simplifies the parallel processing logic compared to implementing complex parallel compression algorithms, while still achieving latency reduction through concurrent decompression of multiple chunks across available cores.
Solution Approach 2:
The patent introduces a work descriptor as an intermediary data structure that manages parallel decompression operations. This descriptor contains all necessary information (source address, destination address, chunk size, core assignment) to coordinate parallel processing without requiring complex inter-core communication logic, thereby reducing overall system complexity while enabling parallel execution.
Data Source
AI summary
An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.