DRAM Cache with Compressed Data and Tag Storage
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Solution Overview
Problem
Large caches require significant tag storage, which is challenging due to the latency penalty of storing tags in DRAM, and maintaining all required address tags in on-chip SRAM is difficult or expensive, especially for storage class memory (SCM) caching, where latency is high and tag storage exceeds practical SRAM capacity.
Innovation Solution
Implementing a system where each DRAM memory module has an extra chip for storing tags and status information, allowing data and associated address tags to be accessed in a single DRAM access, and using compression techniques to store cache lines efficiently within DRAM, with overflow areas for metadata when necessary, to balance access latency with storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tags are stored in DRAM with data, then storage capacity is improved, but access latency increases due to slower DRAM compared to SRAM
Solution Approach 1:
The patent segments the cache into data storage and tag storage components, using a compression circuit to compress cache lines before storage. This segmentation allows tags to be stored efficiently in DRAM alongside data, resolving the contradiction between storage capacity and access latency by organizing storage hierarchically with compression.
Solution Approach 2:
The patent applies compression algorithms that change the parameter of data representation, reducing the size of cache lines and tags. By transforming data into a compressed format, the system can store more tags in DRAM without proportionally increasing access time, as the compression overhead is managed through efficient algorithms.
2Quantity of substance
If compression is applied to cache lines, then storage efficiency is improved, but access time increases due to decompression overhead
Solution Approach 1:
The patent performs compression in advance when cache lines are written to DRAM, so that during read operations, the compressed data is already in storage and only needs decompression. This preliminary compression action reduces the overall time penalty by preparing data in an optimized state before access.
Solution Approach 2:
The patent introduces a compression circuit as an intermediary component between the cache controller and DRAM storage. This intermediary handles the compression and decompression operations, isolating the time overhead from the main data access path and enabling efficient storage without directly impacting critical access timing.
Data Source
AI summary
Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.