Compressed Neural Network Read Thresholds for Memory Degradation

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Solution Overview

Problem

Non-volatile memory devices face challenges in maintaining data integrity due to noise introduced by program disturb and inter-cell interference, leading to voltage level drops over time, which affects the longevity and accuracy of memory cell threshold voltages.

Innovation Solution

A deep neural network (DNN) is used to generate updated read thresholds by compressing the network using pruning, quantization, and Huffman encoding, reducing latency and inference time, thereby accounting for memory cell degradation and improving data retrieval across the lifespan of memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a deep neural network is used to generate read thresholds accounting for memory cell degradation, then data retrieval accuracy is improved, but latency and inference time increase

Engineering Contradiction:
Improveread voltage estimation accuracyVSAvoidinference time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The DNN is segmented into multiple layers with specific functions: input layer receives memory device parameters, hidden layers process degradation patterns, and output layer generates read thresholds. This segmentation allows parallel processing within layers while maintaining sequential depth, reducing overall inference time without sacrificing accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The DNN architecture is made dynamic by implementing early stopping mechanisms and adaptive batch processing. The network can dynamically adjust the number of processing steps based on input complexity, stopping inference early when sufficient accuracy is achieved, thus reducing average inference time while maintaining read voltage estimation precision

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If a deep neural network is used to generate read thresholds accounting for memory cell degradation, then data retrieval accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveread voltage estimation accuracyVSAvoidnetwork architecture complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and isolates the critical degradation compensation function into a specialized DNN module that operates independently from the main memory controller. This extracted DNN focuses solely on analyzing memory degradation patterns and generating corrected read thresholds, simplifying the overall system architecture while maintaining high accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The DNN processes memory device parameters (program/erase cycle counts, retention time, read disturbance history) by transforming them into degraded feature representations. These transformed parameters are then used to generate adjusted read thresholds, effectively changing the parameter space to better represent degradation states without increasing physical device complexity

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If memory cells store higher charge levels to increase capacity, then storage density is improved, but voltage drop due to noise and interference increases

Engineering Contradiction:
Improvecharge stored in cellVSAvoidvoltage drop
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The DNN implements a feedback mechanism by continuously monitoring memory device parameters including program/erase cycle counts, retention time, and read disturbance history. This feedback information is fed into the network to dynamically adjust read thresholds, compensating for voltage drops caused by program disturb and inter-cell interference, thereby maintaining accurate data retrieval despite higher charge storage levels

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20230071837A1Compressing deep neural networks used in memory devices
Publication Date: 2023.03.09 SK HYNIX INC
  • US20230071837A1 patent drawing
  • US20230071837A1 patent drawing
  • US20230071837A1 patent drawing

AI summary

Devices, systems and methods for improving performance of a memory device are described. An example method includes receiving one or more parameters associated with a plurality of previous read operations on a page of the memory device, wherein the previous read operations are based on a plurality of read voltages, determining, using the one or more parameters as an input to a deep neural network comprising a plurality of layers, an updated plurality of read voltages, wherein each of the plurality of layers is a fully connected layer, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device, wherein the deep neural network uses a plurality of weights that have been processed using at least one of (a) a pruning operation, (b) a non-uniform quantization operation, or (c) a Huffman encoding operation.