Compressed Fuse Array Restore for Multi-Core Cache Initialization
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Solution Overview
Problem
As microprocessor complexity increases, the need for configuration and repair data on a multi-core die poses challenges due to real estate and power constraints, with existing fuse arrays being inefficient in storing and providing data, especially after power gating events, which require faster initialization and more data storage.
Innovation Solution
The implementation of a compressed configuration and repair data system using a programmable fuse array that compresses data during fabrication and decompresses it upon power-up/reset, allowing for efficient storage and rapid restoration of configuration and repair data on a multi-core die, utilizing fewer fuses and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data arrays are not persisted across power gating events, then power consumption is reduced during idle periods, but data loss occurs requiring time-consuming recovery operations
Solution Approach 1:
The system performs preliminary actions by persisting data array states to non-volatile storage before power gating events occur. The multi-core processing apparatus saves the state of data arrays in advance, so when power is restored, the data is already available and no recovery operation is needed, thus preventing data loss while maintaining power savings.
Solution Approach 2:
The invention creates copies of data array states and stores them in non-volatile memory. Instead of relying on volatile memory that loses data without power, the system makes redundant copies that survive power gating events, allowing immediate restoration without recovery operations.
2Reliability
If data arrays are persisted to non-volatile storage, then data recovery is enabled after power gating, but access time increases due to non-volatile storage latency
Solution Approach 1:
The data storage system is segmented into multiple levels: frequently accessed data remains in fast volatile memory, while only essential data arrays are persisted to non-volatile storage. This segmentation allows the system to maintain fast access for active data while ensuring recovery capability for persisted data, reducing the overall impact of non-volatile storage latency.
Solution Approach 2:
Different storage media with different characteristics are used for different data types. Volatile memory provides fast access for active data, while non-volatile storage provides reliable persistence for data arrays that need to survive power gating. Each data type is placed in the storage medium that provides the most appropriate balance of speed and reliability for its specific requirements.
3Reliability
If all data arrays are persisted, then complete data recovery is achieved, but storage complexity and overhead increase
Solution Approach 1:
Instead of persisting all data arrays, the system selectively persists only those data arrays that are essential for recovery after power gating events. This partial action approach achieves sufficient reliability for critical data while avoiding the complexity and overhead of persisting every single data array, particularly those that are frequently updated or transient in nature.
Solution Approach 2:
The system dynamically adjusts which data arrays are persisted based on their characteristics, access patterns, and criticality. By changing the parameter of data selection criteria, the system optimizes the balance between recovery completeness and storage complexity, persisting only the necessary data arrays rather than all of them.
Data Source
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AI summary
An apparatus includes a device programmer and a plurality of cores. The programmer programs a semiconductor fuse array with compressed configuration data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and stores decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.