Compressed Inductive Matrix Simulation for Large-Scale Circuit Analysis
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Solution Overview
Problem
Current methods for simulating large integrated circuits face challenges due to the computational and memory-intensive nature of dense inductance matrices, particularly when mutual inductances are considered, leading to inefficiencies and accuracy losses in simulation.
Innovation Solution
A hierarchical approach is employed to compress the inductance matrix by partitioning it into sub-blocks, using Singular Value Decomposition on off-diagonal sub-blocks to reduce them to low-rank format, combined with an iterative method like GMRES for solving the linear system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If direct methods based on matrix factorization are used to solve the linear systems, then the solution accuracy is maintained, but the computational and memory requirements increase quadratically with the dimensions of the matrices
Solution Approach 1:
The patent divides the large inductance matrix into multiple smaller sub-matrices or blocks. By segmenting the matrix, the computational complexity of factorization is reduced from quadratic O(n²) to more manageable levels, while still maintaining solution accuracy through systematic processing of the divided blocks.
Solution Approach 2:
The patent transforms the problem from solving a single large dense matrix system to solving multiple smaller matrix systems in a hierarchical structure. This dimensional transformation allows iterative methods to converge efficiently while maintaining accuracy, avoiding the quadratic complexity of direct factorization methods.
2Productivity
If sparsification techniques are used to reduce the size of the inductance matrix, then the computational efficiency is improved, but the accuracy is lost and the linear system may become unstable
Solution Approach 1:
Instead of applying sparsification to the entire matrix, the patent segments the matrix into blocks and applies selective low-rank compression only to appropriate sub-blocks. This preserves the essential information in each block while reducing overall complexity, maintaining both accuracy and efficiency.
Solution Approach 2:
The patent changes the representation parameter of the inductance matrix from full-rank dense format to low-rank format for certain sub-blocks. This parameter transformation reduces computational complexity while preserving the essential electrical characteristics needed for accurate simulation.
3Device complexity
If model-order reduction techniques are used to simplify the system, then the computational complexity is reduced, but the techniques are not effective for circuits with large number of ports
Solution Approach 1:
The patent divides the large-scale circuit into multiple smaller sub-circuits or blocks, each with fewer ports. Model-order reduction is then applied to each sub-block individually, where it remains effective. The segmented approach allows the technique to scale to large circuits by processing manageable portions systematically.
Solution Approach 2:
After applying model-order reduction to individual sub-blocks, the patent merges the reduced models through hierarchical assembly. This combining process reconstructs the full-circuit behavior from the reduced sub-blocks, achieving both complexity reduction and versatility for large-scale circuits.
4Measurement precision
If the factorization step is performed at every frequency point in the AC analysis, then the solution accuracy is maintained, but the complexity of the analysis increases
Solution Approach 1:
The patent performs preliminary factorization or compression of the matrix structure before AC analysis. This preliminary action prepares the system in advance so that during frequency sweeps, only iterative updates are needed rather than repeated full factorization, maintaining accuracy while reducing time loss.
Solution Approach 2:
Instead of performing factorization at every frequency point, the patent uses periodic or selective updates of the factorized structure. The pre-computed factorization is updated only when necessary, reducing the frequency of expensive operations while maintaining solution accuracy across the frequency spectrum.
Data Source
AI summary
Presented herein are systems, methods, and devices for analyzing a circuit. A netlist is obtained and parsed, where the netlist describes the circuit having one or more branches and one or more nodes. A linear system describing the circuit is obtained and compressed using a hierarchical approach. Compression involves storing off-diagonal sub-blocks in a dense matrix in a low-rank format to reduce the density of the matrix. The linear system is then solved using an iterative operation. An initial guess is used for the voltage at each node and the current through each branch. After performing the first iteration, an initial estimate for the voltage and current is stored and used as the initial guess for the second iteration. The iterative operation is continued until the estimate for the voltage at each node and the current through each branch is sufficiently accurate.