Compressed Logical-to-Physical Table for Memory Subsystems
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Solution Overview
Problem
Memory subsystems face inefficiencies due to the large size of logical-to-physical tables, which lead to high latency and memory overhead when performing address translations, especially with multiple logical addresses involved in memory requests.
Innovation Solution
A compressed logical-to-physical table is generated based on sequential writes, utilizing a sequential write table to identify chunks of logical addresses that have been sequentially written, allowing for efficient read operations by maintaining only a subset of entries in low-latency memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full logical-to-physical table is maintained in memory, then all address translations can be performed, but memory utilization increases and translation overhead increases
Solution Approach 1:
The patent divides the logical-to-physical address translation process into two segments: a compressed table stored in volatile memory for frequently accessed sequential addresses, and a full table stored in non-volatile memory for all addresses. This segmentation allows the system to maintain translation capability for all addresses while reducing volatile memory usage by storing only a portion of the translation data in high-speed memory.
Solution Approach 2:
The patent extracts only the sequentially written portions of the logical-to-physical table into a separate compressed structure in volatile memory. By taking out only the relevant subset of address translations that are likely to be accessed (sequential writes), the system reduces memory overhead while maintaining translation completeness through the full table in non-volatile memory.
2Reliability
If a full logical-to-physical table is maintained in memory, then all address translations can be performed, but translation overhead increases
Solution Approach 1:
The patent applies local quality by optimizing the translation process differently for sequential and non-sequential addresses. For sequential addresses, the system uses a compressed representation with run-length encoding that requires fewer memory accesses. For non-sequential addresses, the system falls back to the full table. This localized optimization reduces translation overhead for the common case of sequential writes while maintaining completeness for all address types.
Solution Approach 2:
The patent performs preliminary action by pre-identifying and compressing sequentially written portions of the logical-to-physical table before they are needed for translation. By detecting sequential write patterns and creating compressed representations in advance, the system reduces translation overhead when these addresses are accessed, as the compressed data is already prepared in volatile memory.
3Quantity of substance
If sequential writes are compressed into a smaller table, then memory utilization decreases, but complexity of managing the compressed table increases
Solution Approach 1:
The patent applies self-service by having the memory controller automatically detect sequential write patterns and manage the compression/decompression of the logical-to-physical table without external intervention. The system monitors write operations, identifies sequential patterns, and dynamically maintains the compressed table structure, reducing the need for complex external management mechanisms while achieving memory optimization.
Solution Approach 2:
The patent changes the representation parameters of the logical-to-physical table by using run-length encoding for sequential portions, transforming the data from a standard one-entry-per-address format to a compressed format that represents multiple consecutive addresses with a single entry. This parameter change reduces memory utilization while the automated detection and management mechanisms handle the increased complexity.
Data Source
AI summary
A method for managing memory addresses in a memory subsystem is described. The method includes determining that a chunk of logical addresses is sequentially written such that a set of physical addresses mapped to corresponding logical addresses in the chunk are sequential. Thereafter, the memory subsystem updates an entry in a sequential write table for the chunk to indicate that the chunk was sequentially written and a compressed logical-to-physical (L2P) table based on (1) the sequential write table and (2) a full L2P table. The full L2P table includes a set of full L2P entries and each entry corresponds to a logical address in the chunk and references a physical address in the set of physical addresses. The compressed L2P table includes an entry that references a first physical address of the first set of physical addresses that is also referenced by an entry in the L2P table.