Compressed LRAID Cache-Line Layout for In-Stripe Parity Storage

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Solution Overview

Problem

Existing memory solutions in large-scale data centers face challenges in achieving reliable, available, and serviceable (RAS) capabilities, particularly in LRAID memory media devices, with inefficient bandwidth utilization and the need for additional memory devices to store parity data.

Innovation Solution

Implementing a CXL-compliant LRAID system with data compression, utilizing a central controller and LRAID circuitry to manage memory operations, including error correction and compression engines, which allows for efficient error detection and correction, and eliminates the need for additional memory devices to store parity data by optimizing data storage within a predetermined number of dice.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If LRAID memory media devices are implemented without data compression, then device complexity is reduced, but bandwidth utilization is inefficient and additional memory devices are required to store parity data

Engineering Contradiction:
Improvebandwidth utilizationVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies data compression algorithms to transform raw data into compressed data, changing the parameter of data size. This allows more data to be stored in the same physical memory space, improving bandwidth utilization without requiring additional memory devices for parity data storage

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent combines data storage and parity data storage into the same memory device by using compression. The compressed data and parity data share the same physical memory resources, eliminating the need for separate dedicated parity storage devices and improving overall system efficiency

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If additional memory devices are used to store parity data, then data reliability is improved, but overhead costs and device complexity increase

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent creates compressed copies of data that occupy less space, allowing parity information to be generated and stored within the same memory device. This copying approach maintains data reliability through redundancy while avoiding the need for additional physical devices

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The memory device is designed to perform multiple functions: storing both data and parity information, and performing both compression and error correction. This multi-functionality eliminates the need for dedicated separate devices for each function, reducing overall system complexity while maintaining reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If data compression is implemented in LRAID systems, then storage efficiency is improved, but manufacturing precision and implementation complexity increase

Engineering Contradiction:
Improvestorage efficiencyVSAvoidimplementation precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent performs data compression before writing data to the memory device, and performs error correction decoding before processing the compressed data. This preliminary action approach ensures that compression and error correction are integrated into the data flow, improving storage efficiency without requiring complex real-time processing during normal operations

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12585542B2Locked raid with compression for memory interconnect applications having a shared cache line
Publication Date: 2026.03.24 MICRON TECHNOLOGY INC
  • US12585542B2 patent drawing
  • US12585542B2 patent drawing
  • US12585542B2 patent drawing

AI summary

Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks (LRAID) including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.