Compressed Mapping Tables for Lower Volatile Memory Use

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Solution Overview

Problem

Memory systems face challenges in efficiently utilizing volatile memory due to its higher cost and less space efficiency compared to non-volatile memory, particularly in storing mapping tables that require significant storage space.

Innovation Solution

Implementing a compressed mapping table in volatile memory with fewer LBAs than PBAs, reducing the amount of information stored by using entries that map subsets of PBAs to one or more LBAs, thereby decreasing the required volatile memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a mapping table is stored in volatile memory, then data access speed is improved, but memory cost and space usage increase

Engineering Contradiction:
Improvedata access speedVSAvoidvolatile memory usage
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies asymmetry by creating an unbalanced mapping relationship where one LBA maps to multiple PBAs. This asymmetric structure allows the mapping table to cover a larger address space with fewer entries, reducing volatile memory requirements while maintaining fast access speeds. The unequal distribution of mapping relationships optimizes the trade-off between access performance and memory consumption.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

Instead of the conventional one-to-one or many-to-one mapping (multiple LBAs to one PBA), the patent inverts the approach by implementing one-to-many mapping (one LBA to multiple PBAs). This inversion reduces the number of mapping entries needed in volatile memory, thereby reducing space requirements while still enabling fast data access through the condensed mapping structure.

Inventive Principle:
Principle #13The other way round (Inversion)

2Adaptability or versatility

If more mapping entries are stored in volatile memory, then address mapping coverage is improved, but memory cost increases

Engineering Contradiction:
Improveaddress mapping coverageVSAvoidvolatile memory usage
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The asymmetric one-to-many mapping relationship allows a single LBA entry to represent multiple PBAs, thereby expanding the address mapping coverage without proportionally increasing the number of volatile memory entries. This asymmetric structure enables the system to handle larger address spaces with limited volatile memory resources.

Inventive Principle:
Principle #4Asymmetry

3Quantity of substance

If volatile memory size is reduced, then cost and space efficiency are improved, but the number of storable entries decreases

Engineering Contradiction:
Improvevolatile memory sizeVSAvoidnumber of storable entries
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

By implementing asymmetric one-to-many mapping where one LBA maps to multiple PBAs, the patent maximizes the information density of each volatile memory entry. This allows the system to maintain comprehensive address mapping coverage with a reduced number of volatile memory entries, thereby reducing memory size requirements while preserving adaptability.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the mapping parameter structure from conventional balanced mappings to an asymmetric one-to-many relationship. This parameter change increases the effective capacity of each volatile memory entry, allowing more address space to be covered with fewer entries, thus reducing the required volatile memory size while maintaining the number of mappable addresses.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260010287A1Data compression for mapping tables
Publication Date: 2026.01.08 MICRON TECHNOLOGY INC
  • US20260010287A1 patent drawing
  • US20260010287A1 patent drawing
  • US20260010287A1 patent drawing

AI summary

Methods, systems, and devices for data compression for mapping tables are described. A memory system may store a table that includes mappings between a set of logical block addresses and a set of physical block addresses. The table may be stored to volatile memory of the memory system and each entry may include a subset of physical block addresses and one or more logical block addresses that correspond to the subset of physical block addresses. In some implementations, a quantity of the entries that each include the subset of physical block addresses and the one or more logical block addresses may be determined based on dividing the set of physical block addresses by a factor. Similarly, a size of the entries may be determined based on dividing the set of physical block addresses by the factor.