Compressed Memory Controller with TLB Translation
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Solution Overview
Problem
As CPU-based systems increase in complexity and performance, the need for additional memory capacity is driven by increased memory requirements, but this often leads to higher costs and physical size increases, while data compression to enhance capacity can degrade CPU performance by increasing memory access times.
Innovation Solution
The implementation of compressed memory controllers that employ line-based, page-based, or hybrid memory capacity compression schemes, using a translation lookaside buffer to efficiently translate physical addresses to physical buffer addresses, allowing for compressed data storage and minimizing the impact on CPU performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data compression is employed to increase effective memory capacity, then memory capacity is improved, but CPU memory access times increase and CPU performance decreases
Solution Approach 1:
The memory system is segmented into multiple memory banks, each with its own compression engine. This allows parallel compression and decompression operations across different banks, reducing the overall time impact on CPU accesses while maintaining high compression ratios for the total memory capacity.
Solution Approach 2:
Data is compressed before being written to memory storage, and decompression is initiated in advance for frequently accessed data patterns. The system pre-loads decompression contexts and maintains translation lookaside buffers (TLBs) that predict and prepare address translations, minimizing the time penalty during actual CPU access operations.
2Quantity of substance
If additional memory capacity is provided in a CPU-based system, then memory requirements are met, but costs and physical area increase
Solution Approach 1:
Multiple memory banks are merged into a unified address space that appears as a single large memory to the CPU. The compression engine merges the storage capacity of multiple physical banks while maintaining the illusion of a larger un compressed memory, effectively doubling or tripling the usable capacity without proportionally increasing physical area.
Solution Approach 2:
The system dynamically changes the compression parameter (compression ratio) based on data patterns and access frequencies. Frequently accessed data uses lower compression ratios for faster access, while less frequently accessed data uses higher compression ratios to maximize capacity utilization, optimizing the balance between effective capacity and access performance.
3Productivity
If translation lookaside buffer is used to translate physical addresses, then translation efficiency is improved, but device complexity increases
Solution Approach 1:
The translation lookaside buffer (TLB) is integrated into the existing memory controller infrastructure, sharing resources with other control functions. The TLB uses the same arbitration logic and address generation units as the main memory controller, eliminating the need for separate dedicated hardware and reducing overall system complexity despite adding translation capability.
Data Source
AI summary
Aspects disclosed herein include memory controllers employing memory capacity compression, and related processor-based systems and methods. In certain aspects, compressed memory controllers are employed that can provide memory capacity compression. In some aspects, a line-based memory capacity compression scheme can be employed where additional translation of a physical address (PA) to a physical buffer address is performed to allow compressed data in a system memory at the physical buffer address for efficient compressed data storage. A translation lookaside buffer (TLB) may also be employed to store TLB entries comprising PA tags corresponding to a physical buffer address in the system memory to more efficiently perform the translation of the PA to the physical buffer address in the system memory. In certain aspects, a line-based memory capacity compression scheme, a page-based memory capacity compression scheme, or a hybrid line-page-based memory capacity compression scheme can be employed.