Compressed Memory Layout With Two-Level Mapping for Low Metadata Overhead
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Solution Overview
Problem
Traditional hardware-based memory compression methods suffer from high metadata overhead and poor data layout, leading to system slowdown and low memory utilization due to inefficient block allocation mechanisms.
Innovation Solution
A hardware-based memory compression approach that divides memory into segments and sub-segments, utilizing two-level address mappings for fast block allocation and reduced metadata overhead, with enlarged sub-segment sizes to increase compression ratio and reduce internal fragmentation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional hardware-based memory compression uses single-level address mapping, then the system is simpler, but the metadata overhead increases and block allocation efficiency decreases
Solution Approach 1:
The patent divides the address mapping into two levels: first-level mapping from virtual addresses to physical addresses, and second-level mapping from physical addresses to compressed block addresses. This segmentation allows each mapping level to be optimized independently, reducing metadata overhead while maintaining fast allocation efficiency.
2Manufacturing precision
If memory is divided into smaller segments, then the granularity of compression is finer, but the metadata overhead increases
Solution Approach 1:
The patent implements a nested structure where segments are divided into sub-segments, and each level has its own mapping table. The first-level mapping table maps segments to physical addresses, while the second-level mapping table maps physical addresses to compressed blocks. This nested approach allows fine-grained compression control while sharing metadata structures across levels, reducing overall overhead.
3Device complexity
If traditional block allocation mechanisms are used, then the implementation is simpler, but memory utilization decreases and system slowdown occurs
Solution Approach 1:
The patent pre-organizes memory into segments and sub-segments with predefined mapping relationships before compression operations begin. The two-level address mapping structure is established in advance, allowing fast block allocation during compression without complex runtime decisions, thereby improving memory utilization and preventing system slowdown.
Data Source
AI summary
A compressed memory is divided into a plurality of segments, each segment is divided into a plurality of sub-segments, and each sub-segment in an uncompressed data space is compressed into block (s) in a compressed data space. Upon a read request to a sub-segment in a segment in compressed memory is received, the corresponding entry is firstly determined based on a first level address mapping between the sub-segment and the entry, and then the corresponding block (s) is determined based on a second level address mapping between the entry and the block (s). By use of two-level address mappings, the size of entry can be reduced, thereby achieving low metadata overhead. Moreover, the proposed data layout for compressed memory.