Cryptographic Hardware Testing with Compressed Private Keys

The patent applies partial action by using a compressed private key that contains only a subset of the full key bits. Instead of exercising all nodes with the complete private key, the invention uses a compressed version that still provides sufficient fault coverage but reduces the number of iterations required, thereby decreasing test time while maintaining acceptable reliability levels.

The patent changes the parameter of the private key by applying compression algorithms that reduce the key size. This parameter change allows the test to achieve adequate node exercise with fewer iterations. The compression ratio can be adjusted to balance between test time and fault coverage requirements, providing a flexible approach to resolving the time-coverage tradeoff.

The patent extracts the testing functionality from the structural scan test approach and implements it as a separate functional test mechanism. Instead of embedding scan chains and additional test circuitry throughout the chip architecture, the invention uses a dedicated test mode that performs functional exercises with compressed keys, thereby achieving high fault coverage without the area overhead of structural scan infrastructure.

The patent makes the cryptographic core circuitry multi-functional by enabling it to operate in both normal cryptographic mode and test mode. The same cryptographic algorithm hardware is used for both production cryptographic operations and for testing purposes with compressed keys. This eliminates the need for separate test-specific circuitry, achieving universal usage that reduces chip area while maintaining test effectiveness.