Compressed Return Address Stack for Recursive Call Prediction
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Solution Overview
Problem
Conventional processor-based systems face performance issues due to limited return address stack size, leading to increased misprediction rates for recursive function calls, which consume all available space and overwrite older entries, negatively impacting system performance.
Innovation Solution
Implementing a compressed return address stack (CRAS) with address and counter fields, where matching return addresses increment counters instead of creating new entries, and a call pattern table to track sequences of return addresses, efficiently handling recursion by collapsing multiple instances into a single entry and tracking recurring sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional return address stack (RAS) is used to store return addresses for recursive function calls, then the processor can predict return addresses, but the limited size of the RAS causes recursive calls to consume all available space and overwrite older entries, increasing misprediction rates
Solution Approach 1:
The patent combines multiple identical return address entries into a single compressed entry that stores the return address along with a counter indicating how many times this address is expected to be used. This merging reduces the number of entries needed in the stack while maintaining prediction accuracy for recursive calls.
Solution Approach 2:
The patent changes the parameters stored in each stack entry from just a return address to a return address paired with a usage counter. This parameter change allows the system to track and compress repeated return addresses, effectively increasing the capacity of the fixed-size stack.
2Reliability
If the RAS size is increased to accommodate more recursive function calls, then misprediction rates decrease, but the device complexity and memory usage increase
Solution Approach 1:
The patent merges multiple RAS operations (push, pop, predict) into a unified compressed stack structure that handles recursive calls more efficiently. This reduces the overall complexity of the RAS management logic while improving prediction reliability.
Solution Approach 2:
The patent introduces dynamic counter fields in the compressed stack entries that automatically adjust based on the frequency of recursive calls. This dynamic adaptation allows the system to optimize its behavior based on actual execution patterns without increasing structural complexity.
3Quantity of substance
If the RAS size is increased to store more return addresses, then more recursive calls can be handled, but the memory usage and resource consumption increase
Solution Approach 1:
The patent merges multiple return address entries into single compressed entries, allowing the same physical memory space to accommodate a much larger number of logical return address slots. This effectively increases the capacity of the RAS without proportionally increasing the physical memory required.
Data Source
AI summary
Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems is disclosed. In one aspect, a processor-based system provides a branch prediction circuit including a CRAS. Each CRAS entry within the CRAS includes an address field and a counter field. When a call instruction is encountered, a return address of the call instruction is compared to the address field of a top CRAS entry indicated by a CRAS top-of-stack (TOS) index. If the return address matches the top CRAS entry, the counter field of the top CRAS entry is incremented instead of adding a new CRAS entry for the return address. When a return instruction is subsequently encountered in the instruction stream, the counter field of the top CRAS entry is decremented if its value is greater than zero (0), or, if not, the top CRAS entry is removed from the CRAS.