Compressible Silicon Alignment Pin for Wafer-to-Wafer Precision
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Solution Overview
Problem
Current methods for fabricating submillimeter-wave and terahertz devices face challenges such as high costs and misalignment issues due to the serial nature of CNC metal machining and difficulties in stabilizing and uniformly depositing thick resist materials like SU-8, as well as electroplating thick layers in LIGA techniques, which affect the precision and alignment of micromachined waveguide components.
Innovation Solution
The development of a compressible silicon alignment pin with an arcuate surface and opposed projections that changes dimensions under mechanical force, allowing for precise alignment of multilayer device components to within 5 μm, and the use of deep reactive ion etching (DRIE) techniques to achieve smooth sidewalls and controlled angles in silicon waveguides, enabling the assembly of compact, low-mass submillimeter-wave heterodyne front-ends and improving wafer-to-wafer alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CNC metal machining is used to fabricate terahertz circuits, then high precision and quality are achieved, but the cost is high and productivity is low due to the serial nature of the process
Solution Approach 1:
The patent replaces traditional mechanical CNC machining with a micromachining process that uses photoresist deposition and plasma etching to fabricate waveguide components. This substitution enables batch fabrication of multiple components simultaneously, dramatically improving productivity while maintaining precision through controlled deposition and etching parameters.
Solution Approach 2:
The patent applies preliminary action by depositing thick photoresist layers (50-200 microns) before machining, which serves as both the structural material and the machining template. This preliminary resist deposition enables subsequent batch processing of multiple waveguide components in parallel, transforming the serial CNC process into a parallel micromachining operation.
2Shape
If thick photoresist materials like SU-8 are used to build waveguide structures, then high aspect ratio features are achieved, but the resist is difficult to deposit uniformly and stabilize, reducing precision
Solution Approach 1:
The patent changes the parameter of photoresist thickness from conventional thin layers to thick layers (50-200 microns), enabling high aspect ratio waveguide structures. This parameter change is achieved through controlled deposition processes that maintain uniformity despite the increased thickness, allowing the formation of tall waveguide walls while preserving layer consistency.
Solution Approach 2:
The patent uses composite material structures by combining thick photoresist layers with metal waveguide components. The photoresist serves dual purposes as both structural support and machining mask, creating a composite system that enables high aspect ratio features while maintaining fabrication precision through the synergistic interaction between the resist and metal layers.
3Manufacturing precision
If LIGA technique with electroplating is used to build metal waveguides, then high precision and arbitrary geometry are achieved, but electroplating thick layers is very difficult and requires additional processing steps
Solution Approach 1:
The patent extracts the electroplating step from the LIGA process, retaining only the photoresist deposition and plasma etching stages. This extraction eliminates the complexity of electroplating thick metal layers while preserving the high precision alignment capabilities, as the photoresist itself serves as the structural material rather than requiring a separate metal deposition step.
Solution Approach 2:
The patent uses disposable thick photoresist structures as temporary forms during fabrication, which are later removed after serving their purpose. These photoresist blocks act as sacrificial elements that enable precise waveguide formation through etching, eliminating the need for complex electroplating while maintaining alignment precision through the photoresist's dimensional stability.
4Productivity
If micromachining techniques are used to fabricate terahertz circuits, then batch fabrication and lower cost are achieved, but alignment precision between wafer layers is difficult to maintain
Solution Approach 1:
The patent implements nested doll by placing alignment features directly within the waveguide structure itself, rather than as separate external elements. The waveguide walls contain embedded alignment marks and geometric features that automatically register with corresponding features on adjacent wafers, enabling precise wafer-to-wafer alignment to within 5 microns while maintaining batch fabrication capability.
Solution Approach 2:
The patent applies self-service by designing waveguide structures with self-aligning geometric features, such as complementary tapered walls and interlocking profiles, that automatically position adjacent wafers correctly during assembly. This self-alignment mechanism eliminates the need for external alignment equipment or complex registration procedures, maintaining high precision while enabling simple batch fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost and improves precision in fabricating terahertz devices by enabling batch fabrication and achieving alignment accuracy comparable to standard metal waveguides, with measured performance showing negligible excess attenuation due to surface roughness and alignment precision better than 1 μm, thus facilitating the development of compact, high-performance submillimeter-wave systems.
Implementation Method 1
the compressible structure configured to assume a compressed configuration upon the application of mechanical force to the two opposed projections
Implementation Method 2
The alignment pin comprises a compressible structure having a central axis
Implementation Method 3
the use of deep reactive ion etching (DRIE) techniques to achieve smooth sidewalls and controlled angles in silicon waveguides
Data Source
AI summary
A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.