Data Compression Accelerator Pipeline for Packet Throughput
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Solution Overview
Problem
General-purpose processors are inefficient in handling high-capacity network and storage workloads, particularly in processing packet streams due to their design not being optimized for such tasks.
Innovation Solution
A highly programmable data processing unit with specialized hardware accelerators, including a hardware-based programmable data compression accelerator that performs history-based compression using a pipeline with a search block, hash block, match block, and path block to efficiently process network packets by replacing repeated strings with references to previous occurrences, followed by entropy coding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose processors are used to process packet streams, then versatility and adaptability are maintained, but processing speed and throughput deteriorate
Solution Approach 1:
The processor is divided into multiple specialized processing units, each handling specific packet processing functions. This segmentation allows parallel processing of multiple packets simultaneously, dramatically improving throughput while maintaining overall system versatility through the combination of different processing units.
Solution Approach 2:
The processing units are designed with multi-functional capabilities to handle various packet processing tasks including compression, decompression, encryption, and protocol handling. This multi-functionality maintains system adaptability while enabling hardware-accelerated performance for each function.
2Productivity
If hardware-based compression accelerators are implemented, then compression speed and throughput are improved, but device complexity increases
Solution Approach 1:
The compression accelerator is integrated as a nested component within the broader data processing unit architecture. The hash block, match block, and output block are hierarchically organized with the hash block containing the hash table, the match block accessing both the hash table and history buffer, creating a nested structure that improves efficiency while managing complexity through modular design.
Solution Approach 2:
The hash block pre-computes hash values and populates the hash table with historical data before the actual compression operation begins. This preliminary action enables the match block to quickly identify potential matches during compression without performing exhaustive searches, significantly improving compression throughput while the pre-computation overhead is managed through efficient hardware implementation.
3Productivity
If multiple byte positions are processed per clock cycle, then compression efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The processing of multiple byte positions per clock cycle is achieved by segmenting the compression pipeline into independent stages (hash block, match block, output block) that can operate in parallel. Each stage handles specific aspects of the compression process, allowing pipelined processing of multiple byte positions simultaneously while managing hardware complexity through modular design.
Solution Approach 2:
The hash table serves as an intermediary data structure that enables efficient comparison of multiple byte positions. By pre-computing and storing hash values in the hash table, the system can quickly identify potential matches across multiple positions without requiring complex real-time comparison logic, thus improving throughput while reducing the precision requirements of the comparison hardware.
Data Source
AI summary
A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a hardware-based programmable data compression accelerator for the data processing unit including a pipeline for performing string substitution. The disclosed string substitution pipeline, referred to herein as a “search block,” is configured to perform string search and replacement functions to compress an input data stream. In some examples, the search block is a part of a compression process performed by the data compression accelerator. The search block may support single and multi-thread processing, and multiple levels of compression effort. In order to achieve high-throughput, the search block processes multiple input bytes per clock cycle per thread.