Data Compression Circuit With Interleaved SRAM Buffering
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Solution Overview
Problem
Current data compression methods in data storage devices are inefficient in managing data blocks, particularly in flash memory-based systems, as they do not effectively utilize buffer memory and fail to optimize data transfer rates and storage space utilization.
Innovation Solution
A method involving a data compression circuit that uses a cache to store data blocks until full, then writes them to a buffer memory using an interleaving method across multiple single-port SRAMs, performing forced encoding regardless of repetitiveness, and utilizing a compressed-data generation circuit to perform literal or length/distance encoding based on comparisons with reference data blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data blocks are stored in cache until full before writing to buffer memory, then data transfer efficiency is improved, but buffer memory access complexity increases
Solution Approach 1:
The buffer memory is segmented into multiple banks (first bank, second bank, etc.) that can be accessed independently. This segmentation allows parallel access to different data blocks, reducing access complexity while maintaining high transfer efficiency. The cache writes data to different banks simultaneously, avoiding sequential access bottlenecks.
Solution Approach 2:
The cache pre-stores data blocks before writing to buffer memory, preparing data in advance for compression operations. This preliminary action allows the compression circuit to process data continuously without waiting for memory access, improving overall data transfer efficiency while managing buffer access complexity through structured bank organization.
2Productivity
If forced encoding is performed on each data block regardless of repetitiveness, then compression processing speed is improved, but encoding complexity increases
Solution Approach 1:
The encoding approach is made dynamic by allowing the system to switch between forced encoding and comparison-based encoding. When data blocks are repetitive, comparison-based encoding is used to achieve better compression. When data blocks are unique or time is critical, forced encoding is applied for faster processing. This dynamic adaptation resolves the contradiction between speed and complexity.
Solution Approach 2:
The encoding parameter (encoding type) is changed based on data characteristics. The system monitors data repetitiveness and adjusts the encoding strategy accordingly. This parameter change allows the system to optimize between processing speed and compression efficiency, managing the complexity-speed tradeoff effectively.
3Quantity of substance
If multiple single-port SRAMs are used with interleaving method, then storage capacity and access efficiency are improved, but memory system complexity increases
Solution Approach 1:
The buffer memory is divided into multiple single-port SRAM banks with interleaved addressing. Each bank handles specific address ranges, allowing parallel access to different data blocks. This segmentation increases storage capacity while managing complexity through regular, predictable access patterns that simplify control logic.
Solution Approach 2:
The memory system adds a bank dimension to the storage architecture. Instead of accessing one large memory sequentially, the system distributes data across multiple banks in an interleaved pattern, accessing them in parallel. This dimensional change from single-memory sequential access to multi-memory parallel access improves capacity and efficiency while keeping individual bank complexity low.
4Speed
If reference data blocks are read simultaneously from buffer memory based on address, then comparison speed is improved, but memory read complexity increases
Solution Approach 1:
Reference data blocks are read from the buffer memory in advance before the actual compression comparison operation. By pre-reading and storing reference blocks in the cache, the system prepares comparison data ahead of time, enabling faster real-time comparison operations without increasing memory read complexity during critical processing phases.
Data Source
AI summary
A method of operating a data compression circuit includes receiving and storing a plurality of data blocks until a cache is full and writing the data blocks that have been stored in the cache to a buffer memory when the cache is full. The method also includes performing forced literal/literal encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full.