Compression Interface Circuit for Multi-Scheme ISA Support

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Solution Overview

Problem

Existing data processing systems face challenges in efficiently supporting various data compression schemes without requiring modifications to the instruction set architecture (ISA) and managing obsolete techniques, which can occupy valuable encoding space.

Innovation Solution

The implementation of compression circuitry that communicates through a generic interface with processing circuitry, using identification data to determine compatible compression schemes, allowing for flexible support of multiple compression methods without altering the ISA, and providing instructions for context switching and data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple compression schemes are supported through ISA modifications, then compression functionality is improved, but device complexity and ISA space consumption increase

Engineering Contradiction:
Improvecompression scheme supportVSAvoidISA space
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A compression controller acts as an intermediary between the processing circuitry and multiple compression circuits. The controller receives compression scheme identification from the processor, selects the appropriate compression circuit, and manages the compression operation. This mediator approach allows multiple compression schemes to be supported without modifying the ISA, as the processor only needs to communicate through the standard interface defined by the controller.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The compression controller provides a universal interface that can manage multiple different compression circuits (first compression circuit, second compression circuit, etc.). Each compression circuit can implement different compression schemes, but they all access the processor through the same standardized interface. This multi-functionality allows the system to support various compression schemes while maintaining a simple, unchanged ISA.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If compression circuits are integrated into the processor, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improvedata processing speedVSAvoidprocessor structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The compression functionality is segmented into separate, independent compression circuits rather than being integrated into the main processor core. The first compression circuit and second compression circuit are distinct functional units that can operate independently. The compression controller manages these segmented components, allowing them to be integrated at the system level while maintaining clear separation of functions, thus improving speed without excessively increasing processor core complexity.

Inventive Principle:
Principle #1Segmentation

3Stability of the object's composition

If obsolete compression schemes are maintained in the ISA, then backward compatibility is improved, but encoding space is wasted

Engineering Contradiction:
Improvebackward compatibilityVSAvoidencoding space
Core Design Contradiction:
Stability of the object's compositionVSQuantity of substance

Solution Approach 1:

Instead of maintaining obsolete compression schemes in the ISA, the system uses the compression controller to emulate or copy the functionality of legacy compression schemes. The controller can interpret compression scheme identification and route to appropriate circuits, effectively copying the behavior of old schemes without requiring dedicated ISA encoding space for each obsolete format. This allows backward compatibility through software/controller emulation rather than hardware/ISA duplication.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20260019090A1Circuitry and method
Publication Date: 2026.01.15 ARM LTD
  • US20260019090A1 patent drawing
  • US20260019090A1 patent drawing
  • US20260019090A1 patent drawing

AI summary

Circuitry comprises instruction decoder circuitry to decode instructions for execution; processing circuitry to execute instructions decoded by the instruction decoder circuitry; interface circuitry defining an interface for data communication with data compression circuitry; in which the processing circuitry is responsive to one or more instructions of an instruction set defined for the processing circuitry to provide to the interface: input data to be processed by the data compression circuitry; and identification data identifying a compression system for use by the data compression circuitry to process the input data; and in which the processing circuitry is configured to receive from the interface: status data indicating whether data compression circuitry connected to the interface can process data using the compression system identified by the identification data; and, when the status data indicates that the data compression circuitry can process data using the compression system identified by the identification data, output data which has been processed from the input data by the data compression circuitry using the compression system identified by the identification data.