Compression Search Block Striping for High-Throughput Data Matching
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Solution Overview
Problem
General-purpose processors are inefficient in handling high-capacity network and storage workloads, particularly in processing packet streams due to their poor performance in data compression and stream processing.
Innovation Solution
A highly programmable data processing unit with specialized hardware accelerators, including a data compression pipeline that performs history-based compression using a search block, hash block, match block, and path block to efficiently compress data streams by replacing repeated byte strings with references to previous occurrences, followed by entropy coding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If general-purpose processors are used for data compression and stream processing, then device versatility is maintained, but processing speed and throughput deteriorate
Solution Approach 1:
The processor is divided into general-purpose processing cores and specialized hardware accelerators. The hardware accelerators are further segmented into functional blocks including a data compression pipeline with search block, hash block, match block, and path block. This segmentation allows specific compression tasks to be handled by dedicated hardware while general-purpose cores handle other operations, resolving the contradiction between speed and complexity.
Solution Approach 2:
Hardware accelerators serve as intermediary components between the general-purpose processing cores and the data compression functions. These accelerators include specialized blocks (search block with hash table, match block with history buffer) that mediate the compression process, providing high-speed processing without requiring the general-purpose cores to directly perform compression operations.
2Productivity
If hardware accelerators are added to improve compression throughput, then processing capacity increases, but device complexity increases
Solution Approach 1:
The hardware accelerators are designed with multi-functional blocks that can perform various compression operations. The search block can search for patterns in the history buffer, the hash block can compute hash values for different window sizes, and the match block can perform both forward and backward matching. This universality allows a single hardware accelerator to handle multiple compression scenarios, improving throughput without proportionally increasing complexity.
3Loss of substance
If larger history buffers are used to improve compression ratio, then compression efficiency increases, but memory access time and complexity increase
Solution Approach 1:
The history buffer is segmented into multiple banks, allowing parallel access to different portions of the buffer. The match block can simultaneously search multiple banks, reducing the effective access time even though the total buffer size is large. This segmentation resolves the contradiction between maintaining large history buffers for better compression ratios and minimizing memory access time.
4Productivity
If multiple byte positions are processed per clock cycle to improve throughput, then processing speed increases, but complexity of the processing pipeline increases
Solution Approach 1:
The hardware accelerator processes multiple byte positions in a periodic manner, with each clock cycle handling a fixed number of positions (e.g., 4 positions per cycle). The pipeline is organized to systematically advance through the input data stream, processing predetermined numbers of byte positions at regular intervals. This periodic processing approach improves throughput while keeping the pipeline complexity manageable through regular, predictable operation patterns.
Data Source
AI summary
A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a hardware-based programmable data compression accelerator for the data processing unit including a pipeline for performing string substitution. The disclosed string substitution pipeline, referred to herein as a “search block,” is configured to perform string search and replacement functions to compress an input data stream. In some examples, the search block is a part of a compression process performed by the data compression accelerator. The search block may support single and multi-thread processing, and multiple levels of compression effort. In order to achieve high-throughput, the search block processes multiple input bytes per clock cycle per thread.