Compression Search Pipeline for Multi-Byte Packet Stream Throughput
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Solution Overview
Problem
General-purpose processors are inefficient in handling high-capacity network and storage workloads, particularly in processing packet streams due to their design not being optimized for such tasks.
Innovation Solution
A highly programmable data processing unit with specialized hardware accelerators, including a hardware-based programmable data compression accelerator that performs history-based compression using a pipeline with a search block, hash block, match block, and path block to efficiently process network or storage packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose processors are used to process packet streams, then device versatility is maintained, but processing speed and throughput deteriorate
Solution Approach 1:
The processor is divided into multiple processing cores, each capable of independently processing packet streams. This segmentation allows parallel processing of multiple data flows simultaneously, thereby increasing overall throughput while maintaining the versatility of general-purpose processing through programmable cores.
Solution Approach 2:
The processing cores are designed as multi-functional units that can handle various packet processing tasks including classification, filtering, routing, and compression. This universality allows a single processor architecture to perform diverse network functions without sacrificing processing efficiency.
2Device complexity
If general-purpose processors handle high-capacity network workloads, then device complexity remains low, but processing capacity and efficiency deteriorate
Solution Approach 1:
The system transitions from single-thread sequential processing to multi-thread parallel processing across multiple cores. This dimensional change in processing architecture enables the system to handle high-capacity network workloads by distributing processing tasks across multiple execution units, thereby scaling processing capacity without proportionally increasing device complexity.
3Device complexity
If compression search is performed sequentially at one byte position per clock cycle, then algorithm simplicity is maintained, but compression throughput deteriorates
Solution Approach 1:
The compression search algorithm is segmented into multiple independent search threads, each processing different byte positions in parallel. The hash table is divided into multiple banks that can be accessed simultaneously by different threads, enabling multi-byte-position search per clock cycle while maintaining the fundamental simplicity of the LZW compression algorithm.
Solution Approach 2:
The hash table is pre-computed and organized into multiple banks before the compression process begins. This preliminary organization allows search threads to quickly access potential match positions without sequential scanning, thereby increasing compression throughput while keeping the algorithm structure relatively simple.
Data Source
AI summary
A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a hardware-based programmable data compression accelerator for the data processing unit including a pipeline for performing string substitution. The disclosed string substitution pipeline, referred to herein as a “search block,” is configured to perform string search and replacement functions to compress an input data stream. In some examples, the search block is a part of a compression process performed by the data compression accelerator. The search block may support single and multi-thread processing, and multiple levels of compression effort. In order to achieve high-throughput, the search block processes multiple input bytes per clock cycle per thread.