Compression Status Bit Cache and Off-Chip Backing Store
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Solution Overview
Problem
As data processing systems increase in performance and memory capacity, the need to store compression status bits on-chip becomes costly in terms of die area, making it challenging to support large amounts of attached storage without incurring significant die area expenses.
Innovation Solution
A memory system that determines and updates compression status for virtually addressed units, utilizing a memory management unit to access page table entries with compression cache tags, allowing the compression status bits to be stored off-chip in attached memory, thereby reducing the need for on-chip storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If compression status bits are stored in on-chip RAM to enable fast access and determine compression status before memory access requests, then memory access performance is improved, but die area cost increases significantly when attached memory capacity is doubled
Solution Approach 1:
The patent segments the compression status bit storage into two parts: a small on-chip compression status bit cache for frequently accessed blocks, and a larger off-chip compression status bit backing store in attached memory for the complete address space. This segmentation allows the system to maintain fast access performance for working sets while avoiding the prohibitive die area cost of storing all compression status bits on-chip.
Solution Approach 2:
The patent introduces a compression status bit cache as an intermediary between the memory interface circuitry and the full compression status bit backing store. The cache sits between the fast on-chip resources and the slow off-chip storage, providing a buffer that delivers fast access performance while allowing the majority of data to reside in cheaper off-chip memory.
2Reliability
If a large compression status RAM is implemented on-chip to support large amounts of attached memory, then all compression status bits can be accessed quickly, but the die area becomes prohibitively expensive
Solution Approach 1:
The patent divides the compression status bit storage into a small on-chip cache portion and a large off-chip backing store portion. The on-chip cache holds compression status bits for currently active or frequently accessed memory blocks, ensuring reliability and fast access for working sets. The off-chip backing store holds the complete set of compression status bits for the entire attached memory address space.
Solution Approach 2:
The patent accepts that off-chip memory access is slower and uses the off-chip backing store as a cheaper, lower-speed storage medium for compression status bits. The system tolerates occasional slower access when compression status bits must be fetched from off-chip memory, in exchange for dramatically reduced die area costs.
3Area of stationary object
If compression status bits are stored off-chip to reduce die area costs, then die area is reduced, but access time increases due to off-chip memory latency
Solution Approach 1:
The patent pre-loads compression status bits into the on-chip cache before they are needed for memory access requests. The memory interface circuitry or memory management unit can proactively fetch compression status bits into the cache when anticipating future access patterns, or load them when blocks are first accessed, so that subsequent accesses find the data already in the fast on-chip cache.
Solution Approach 2:
The patent maintains the on-chip compression status bit cache continuously populated with relevant compression status information through background loading and caching operations. This ensures that the cache remains useful and reduces the frequency of slow off-chip accesses, maintaining continuous high-performance operation for the active working set of memory blocks.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.