Compressive Interlayer and Barrier for Power Metallization
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Solution Overview
Problem
Semiconductor devices face cracking issues due to thermal stress at metallization edges, particularly when thick, stiff metal layers are used, leading to tensile stresses in the substrate, which can result in cracks during cooling processes.
Innovation Solution
A structured interlayer with compressive residual stress is implemented, extending beyond the metallization edges by at least 0.5 microns, counteracting tensile stresses and preventing ion diffusion through a barrier layer, thereby reducing crack probability without altering the temperature profile or metallization properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick and stiff metallization stacks are used to improve thermal performance, then thermal performance is improved, but tensile stress at metallization edges increases causing cracks
Solution Approach 1:
The patent applies counterweight principle by introducing a compressive stress layer (e.g., silicon nitride) that generates compressive stress to counterbalance the tensile stress generated by the thick metallization stack during thermal cycling. This stress compensation prevents crack formation at metallization edges while maintaining the thermal performance benefits of the thick metal layer.
Solution Approach 2:
The patent uses composite material structure by combining the thick metallization stack with a compressive stress layer (such as silicon nitride) to create a multi-layer composite structure. This composite approach allows the system to simultaneously achieve high thermal conductivity from the metal and crack resistance from the compressive stress layer, resolving the contradiction between thermal performance and crack resistance.
2Strength
If temperature budget is reduced after metal deposition to avoid cracks, then crack formation is reduced, but device processing flexibility is limited
Solution Approach 1:
The patent applies preliminary action by forming the compressive stress layer (e.g., silicon nitride) before depositing the thick metallization stack. This pre-formed layer is specifically designed to generate compressive stress that will counterbalance the tensile stress that will later develop during thermal cycling, allowing subsequent high-temperature processing without crack formation and maintaining full temperature budget flexibility.
3Strength
If metals with reduced stiffness are used to avoid cracks, then crack resistance is improved, but thermal performance deteriorates
Solution Approach 1:
The patent applies segmentation by separating the thermal management function from the stress management function. The thick metallization stack (Cu, Al, or Au) is dedicated to thermal conduction, while a separate compressive stress layer (silicon nitride) is dedicated to stress compensation. This functional segmentation allows each layer to be optimized independently - the metal for thermal performance and the dielectric for crack resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces stress at the metallization edges, minimizing crack formation in the substrate and enhancing the reliability of semiconductor devices by using a compressive interlayer and barrier to manage thermal stresses and ion contamination.
Implementation Method 1
the structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer
Implementation Method 2
a barrier on the structured power metallization and configured to prevent diffusion of at least one of dipole molecules (such as water, moisture), positive and negative ions such as water ions (e.g. hydroxide), metal ions (e.g. sodium ions, potassium ions or calcium ions), chloride ions, sulphur ions, and fluoride ions towards the structured power metallization
Data Source
AI summary
A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.