Compressive Strain Layer for Wafer Bowing Control
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Solution Overview
Problem
The production of semiconductor devices often results in wafer bowing due to stresses generated by applied layer sequences, which complicates further processing and requires solutions to prevent or mitigate this issue.
Innovation Solution
A semiconductor device with a compressively stressed layer made from materials like Ta, Mo, or Nb, or their compounds, applied over a semiconductor body, extending up to the edge of the device, which can be electrically conductive or insulating, and used to establish connections or provide insulation, and a method involving sputtering to set the stress and apply these layers extensively over the workpiece before separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heterogeneous layer sequences are applied by heteroepitaxy or metallic/conductive/insulating layers, then functional layers are created, but wafer bowing occurs making further processing difficult
Solution Approach 1:
A compressively stressed layer is applied before the heterogeneous layer sequence to pre-compensate for the tensile stresses that will be generated during subsequent processing. This preliminary counter-stress prevents wafer bowing from occurring in the first place, maintaining wafer flatness throughout the manufacturing process while still allowing functional layers to be applied.
Solution Approach 2:
The patent changes the stress parameter of the wafer structure by introducing a compressively stressed layer with specific stress characteristics. This parameter change (from tensile to compressive stress) counteracts the stress imbalances caused by heterogeneous layer sequences, thereby controlling wafer flatness without compromising the functionality of subsequent layers.
2Manufacturing precision
If compressively stressed layers are applied to reduce wafer bowing, then wafer flatness is improved, but the layer adds complexity to the device structure
Solution Approach 1:
The compressively stressed layer is designed to serve multiple functions simultaneously: it provides stress compensation to maintain wafer flatness, acts as an adhesive layer for subsequent heterogeneous layers, and can function as an electrical contact or barrier layer depending on material selection. This multi-functionality reduces the need for additional separate layers, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent combines the stress compensation function with other layer functions by selecting materials that provide both mechanical stress control and electrical/functional properties. For example, a metallic compressively stressed layer can simultaneously provide stress compensation and electrical connectivity, merging multiple functions into a single layer to minimize structural complexity.
3Manufacturing precision
If the compressively stressed layer extends to the edge of the semiconductor device, then stress compensation is maximized, but the layer may interfere with separation processes
Solution Approach 1:
The compressively stressed layer is applied with varying thickness or composition across different regions of the wafer. In central regions where stress compensation is most needed, the layer extends fully to maximize effectiveness. In edge regions where separation is required, the layer thickness is reduced or its composition is modified to minimize interference with separation processes, thereby achieving local optimization of both stress compensation and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compressively stressed layers effectively reduce wafer bowing, provide electrical connections, and act as current spreading structures, while being corrosion-resistant, allowing for efficient processing and reduced damage during separation, and can be used to adjust the bowing direction.
Implementation Method 1
A first compressively stressed layer over a semiconductor body... These stresses may lead to bowing of the wafer... The compressively stressed layers effectively reduce wafer bowing
Implementation Method 2
The compressively stressed layer may be applied by sputtering. A stress in the compressively stressed layer may be set by setting the sputtering rate.
Data Source
AI summary
A semiconductor component may include a first compressive strain layer on top of a semiconductor body. A material for the first compressive strain layer may include Ta, Mo, Nb, compounds thereof, and combinations thereof.