Compressive Stress Patterns in Semiconductor Devices
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Solution Overview
Problem
The increasing complexity of semiconductor devices requires improved integration density, reliability, and multi-functional characteristics, particularly in semiconductor memory devices, which existing technologies have not adequately addressed.
Innovation Solution
The method involves forming gate patterns on a substrate with NMOS and PMOS transistor regions, creating spacer structures, etching recessed regions, and applying compressive and tensile stress patterns to enhance carrier mobility and electrical characteristics, including the use of mask oxide layers and metal-semiconductor compound layers to manage leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased to meet industry requirements, then device functionality and speed improve, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent applies different stress conditions to different regions of the semiconductor device. Tensile stress patterns are applied to the NMOS transistor region while compressive stress patterns are applied to the PMOS transistor region. This local differentiation optimizes carrier mobility for each transistor type independently, allowing high integration density while maintaining manufacturing precision through region-specific optimization rather than uniform processing
Solution Approach 2:
The patent changes the physical and chemical parameters of the semiconductor structure by introducing stress patterns through specially designed layers and structures. By modifying the stress state (a physical parameter) in different transistor regions, the patent improves electrical characteristics and carrier mobility without compromising manufacturing precision, even as integration density increases
2Reliability
If stress patterns are applied to enhance carrier mobility, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
The patent segments the semiconductor device into distinct NMOS and PMOS transistor regions, each receiving appropriate stress patterns. By dividing the device into functional segments with specific stress requirements, the patent improves electrical characteristics through targeted stress application while managing overall device complexity through systematic regional differentiation rather than uniform complex processing
Solution Approach 2:
The patent employs composite material structures to generate stress patterns, such as combining different semiconductor materials or using stress-inducing layers alongside active transistor regions. This approach improves carrier mobility and electrical characteristics by incorporating materials with different mechanical properties, while the composite structure itself becomes an integrated part of the device architecture rather than an added complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and electrical characteristics by optimizing stress patterns and layer formations, reducing leakage current and voids between transistors, thereby enhancing integration density and device performance.
Implementation Method 1
forming a compressive stress pattern in the recessed region, a portion of a sidewall of the compressive stress pattern protruding upwardly from a upper surface of the substrate
Data Source
AI summary
Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.