4-to-2 Compressor Circuit Using Bitwise Inverted Representation
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Solution Overview
Problem
Existing circuits for adding multiple binary numbers, such as those using 3-to-2-compressors in pass transistor logic, consume a large surface area and require additional inverters, which slows down the process and increases area consumption.
Innovation Solution
A 4-to-2-compressor circuit is designed with a first and second sub-circuit that transmit bitwise inverted representations of three binary numbers, reducing the need for additional inverters and allowing for a more compact layout by using XNOR, AND, and NOR circuits within bit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 3-to-2-compressors are implemented in pass transistor logic, then the addition speed is improved, but the surface area consumption increases
Solution Approach 1:
The patent inverts the logic levels of signals within the pass transistor logic circuit by strategically placing inverters at specific nodes. This inversion technique allows the circuit to maintain fast pass transistor switching while reducing the total number of transistors required, thereby decreasing surface area consumption while preserving addition speed
Solution Approach 2:
The patent changes the logic level parameters of intermediate signals by using inverters to complement signals at critical points in the circuit. This parameter transformation enables the compression function to be achieved with fewer transistors, reducing area while maintaining the high-speed performance characteristic of pass transistor logic
2Stability of the object's composition
If additional inverters are added to maintain logic levels, then the logic level stability is improved, but the addition speed decreases
Solution Approach 1:
The patent applies preliminary action by pre-inverting signals at specific points within the circuit path. Instead of adding inverters at the output to correct logic levels, the inversion is performed earlier in the signal flow, allowing subsequent stages to operate with the correct logic levels without requiring additional speed-reducing inverters at critical paths
Solution Approach 2:
The patent uses strategically placed inverters as intermediary elements that transform signal logic levels at optimal points in the circuit. These intermediary inverters are positioned where they can stabilize logic levels for downstream stages without being in the critical path of the addition operation, thus avoiding speed penalties
3Stability of the object's composition
If additional inverters are added to maintain logic levels, then the logic level stability is improved, but the area consumption increases
Solution Approach 1:
The patent merges the function of logic level stabilization with the existing compression logic by integrating inverters into the compression circuit structure itself. Rather than adding separate inverter stages, the inversion function is combined with the compression operation, achieving logic level stability without proportionally increasing area consumption
Data Source
AI summary
A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.