Compressor Circuit Reduces SRAM Test Area and Delay
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Solution Overview
Problem
Conventional SRAM test systems suffer from increased circuit area and signal delay due to the presence of numerous latches and multiplexers in the scan chain.
Innovation Solution
A test system comprising a compressor circuit that compresses X-bit signals from first latches to Y-bit signals, where X > Y, and at least one second latch to generate a scan output, forming D flip-flops, which operates differently in normal and test modes to reduce circuit area and signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a scan chain comprising a large number of latches and multiplexers is used to test SRAM, then the test function can be performed, but the circuit area increases and signal delay increases
Solution Approach 1:
The patent merges the test function with the normal output function by using the same latch structure for both purposes. The latch array serves dual functions: storing data for normal operation and capturing test results, eliminating the need for separate test-specific latches and reducing overall circuit area
Solution Approach 2:
The latch structure is designed to be universal, serving both normal memory operation and test functions. The same latches that store operational data also capture test results, and the same output circuitry handles both normal data output and test result output, achieving multi-functionality with minimal additional components
2Reliability
If a scan chain comprising a large number of latches and multiplexers is used to test SRAM, then the test function can be performed, but the signal delay during scanning increases
Solution Approach 1:
The patent extracts the test result capture function from the traditional scan chain structure. By using the existing latch output to directly capture test results without requiring them to propagate through the entire scan chain, the method removes unnecessary delay paths while maintaining test functionality
Solution Approach 2:
The latches are designed to preliminarily capture test results during the test operation, storing them in a ready state before final output. This preliminary capture action allows test results to be obtained without waiting for complete scan chain propagation, reducing overall test time and signal delay
Data Source
AI summary
A system, comprising: a plurality of first latches; a compressor circuit, coupled to the first latches, configured to compress an first signal having X bits from the first latches to a second signal having Y bits, wherein X and Y are positive integers and X is larger than Y; and at least one second latch, coupled to the compressor circuit, configured to receive the second signal to generate a scan output, wherein each of the first latches and the second latch forms a D flip flop. The system outputs the first signal but none of the scan output in a normal mode, and outputs the scan output but none of the first signal in a test mode.