Compressor Circuit Gating for Low-Power Wallace Tree Multipliers
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Solution Overview
Problem
Existing compressor circuits in AI chips experience high power consumption and delay, particularly in small numerical operations.
Innovation Solution
A compressor circuit design that includes a first full adder, a second full adder, and selection circuits to control the operation of the second full adder based on input signals and selection signals, allowing the second full adder to be turned off when the most significant bit is low, thereby reducing energy consumption and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second full adder is always operated in the compressor circuit, then the circuit can handle all input signal combinations, but power consumption and delay increase
Solution Approach 1:
The patent applies dynamic operation control to the second full adder by using a control signal generated from the most significant bit of the four input signals. When the most significant bit indicates small numerical operation (both output of first full adder and most significant bit are low level), the second full adder is turned off to save power. When larger operations are detected, the second full adder is activated. This dynamic switching resolves the contradiction between maintaining full circuit functionality and reducing power consumption.
2Reliability
If the second full adder is always operated in the compressor circuit, then the circuit can handle all input signal combinations, but delay increases
Solution Approach 1:
The patent dynamically controls the operation of the second full adder based on the magnitude of input signals detected through the most significant bit. By turning off the second full adder during small numerical operations (when both first full adder output and most significant bit are low level), the propagation delay is significantly reduced. The control mechanism ensures that the second full adder is only activated when larger operations require its full adding capability, thus resolving the contradiction between handling all input combinations and minimizing delay.
3Device complexity
If the compressor circuit uses existing full adder design without selection control, then the circuit structure is simple, but energy consumption and delay are high
Solution Approach 1:
The patent introduces dynamic control mechanisms (selection circuits and control signals) to the compressor circuit while maintaining relatively simple overall structure. The control signal is generated from existing most significant bit signals without requiring complex additional logic. This dynamic approach allows the second full adder to be selectively activated only when needed, resolving the contradiction between structural simplicity and energy efficiency by adding minimal control overhead for significant power savings.
Data Source
AI summary
The present disclosure provides a compressor circuit, a Wallace tree circuit, a multiplier circuit, a chip and an apparatus. The compressor circuit includes a first full adder, a second full adder, and a first selection circuit. An output end of the first full adder is connected to an input end of the first selection circuit, and an output end of the first selection circuit is connected to an input end of the second full adder. The first selection circuit is configured to determine an input signal output by the first selection circuit to the second full adder according to a first selection signal; and the input signal output by the first selection circuit to the second full adder and a most significant bit signal of a plurality of input signals of the compressor circuit are used to control turning on and turning off of the second full adder, which can reduce circuit power consumption and delay.