Computational Cache for State Vector RMW Operations
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Solution Overview
Problem
The existing cache systems in integrated circuits (ICs) face performance degradation due to high access latencies and low bandwidth in Dynamic Random Access Memory (DRAM), particularly when performing read-modify-write (RMW) operations on state vectors, which leads to processor stalls and underutilization of DRAM bandwidth.
Innovation Solution
A cache system with a computational cache and a miss-handler that performs RMW operations autonomously, caching state vectors and handling cache misses to reduce processor involvement and improve memory access efficiency, enabling high-speed RMW operations without processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If state vectors are stored in DRAM, then large volume of state vector information can be maintained, but access latency increases and system performance decreases
Solution Approach 1:
The memory system is segmented into two distinct parts: a high-speed computational cache memory for frequently accessed state vectors and a high-capacity DRAM memory for bulk storage. This segmentation allows the system to maintain large volumes of state vectors in DRAM while providing fast access to commonly used vectors through the cache, thereby resolving the contradiction between storage capacity and access speed.
Solution Approach 2:
A computational cache memory acts as an intermediary between the processor and DRAM. This intermediary layer stores copies of frequently accessed state vectors and handles read-modify-write operations autonomously, reducing the time the processor waits for memory operations while maintaining the ability to store large volumes of data in DRAM.
2Ease of operation
If processor performs read-modify-write operations on state vectors, then state vector updates can be performed, but processor stalls during memory access time
Solution Approach 1:
The computational cache memory is equipped with autonomous computational logic that can perform read-modify-write operations independently without processor intervention. When the processor issues an RMW command, the cache memory autonomously retrieves the state vector, performs the modification, and writes it back, eliminating processor stalls while maintaining full update capability.
Solution Approach 2:
The system performs preliminary actions by pre-loading state vectors into the computational cache memory before they are needed by the processor. This allows the cache to have the data ready for immediate autonomous RMW operations, preventing processor stalls and maintaining operational capability.
3Reliability
If processor waits for DRAM operations to complete, then data consistency is maintained, but DRAM bandwidth is underutilized
Solution Approach 1:
The computational cache memory enables continuous useful action by autonomously handling RMW operations without requiring the processor to wait for DRAM operations to complete. The cache maintains data consistency through its autonomous operation while the processor continues executing other tasks, thereby maximizing DRAM bandwidth utilization without sacrificing data consistency.
Solution Approach 2:
The computational cache acts as an intermediary that buffers between the processor and DRAM, allowing the processor to issue commands and continue execution while the cache handles data retrieval and modification autonomously. This intermediary layer maintains data consistency while eliminating processor stalls and maximizing DRAM bandwidth utilization.
4Adaptability or versatility
If random state vector accesses are performed, then flexible data access is achieved, but DRAM bandwidth is penalized and system performance degrades
Solution Approach 1:
The memory system is segmented into a computational cache for random access operations and DRAM for bulk storage. The cache's fast access time compensates for its smaller capacity, allowing flexible random access to state vectors without penalizing DRAM bandwidth, thereby maintaining both access flexibility and system performance.
Solution Approach 2:
The computational cache serves as an intermediary that handles random access operations autonomously, protecting the DRAM from the performance penalty of random accesses. The cache's proximity to the processor and autonomous computational capability allow flexible data access patterns while maintaining high system performance.
Data Source
AI summary
A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.