Computational Memory Circuit Design for In-Memory Computing
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Solution Overview
Problem
Existing circuit conception tools face difficulties in designing computational memory circuits for In-Memory Computing (IMC) and Near-Memory Computing (NMC) architectures, particularly in silicon qualification and adaptability to specific application requirements, leading to inefficiencies in energy consumption and performance.
Innovation Solution
A method for circuit conception that evaluates and selects the most suitable memory cell type based on instruction frequency and storage size, determining minimum and maximum operating frequencies to optimize energy efficiency and performance, involving the use of various SRAM cell types such as 1RW, 1R1W, 2RW, and 4RW cells, and generating digital design files for implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing circuit conception tools are used for IMC/NMC architectures, then standard memory cell designs can be generated, but silicon qualification and adaptability to specific application requirements are insufficient
Solution Approach 1:
The circuit conception tool dynamically adapts to different application requirements by accepting custom parameters including instruction set architectures, memory access patterns, and performance targets. The tool adjusts memory cell type selection, bitcell matrix configuration, and peripheral circuit design based on these dynamic inputs, enabling silicon-qualified designs for specific IMC/NMC applications rather than using fixed standard designs
Solution Approach 2:
The tool enables parameter customization at multiple levels: memory cell type (1RW, 1R1W, 2RW, 2R1W, 4RW), bitcell matrix dimensions, wordline/bitline configurations, and peripheral circuit parameters. These parameter changes allow the design to be optimized for specific application requirements while maintaining silicon manufacturability through controlled variation of proven design parameters
2Productivity
If data transfer between memories and processing elements is performed externally, then memory capacity and processing power can be increased, but energy consumption increases significantly
Solution Approach 1:
The design merges memory storage functions with computational functions by integrating ALU units directly within the memory array structure. Memory cells are configured to perform arithmetic and logic operations on stored data without requiring external data transfer, combining the benefits of high-capacity memory with energy-efficient in-memory computing
Solution Approach 2:
Peripheral circuits serve as intermediaries between the memory array and external processing elements, enabling complex memory operations to be performed locally. These intermediary circuits handle data preprocessing, postprocessing, and control functions within the memory device, reducing the need for high-energy external data transfers while maintaining system productivity
3Speed
If memory access operations are simplified, then operating speed can be increased, but the number of read/write operations per cycle is reduced
Solution Approach 1:
The memory array is segmented into multiple independently controllable banks or regions, each capable of simultaneous access. This segmentation allows multiple read/write operations to occur in parallel across different segments while maintaining simplified access protocols within each segment, achieving both high speed and high operations-per-cycle throughput
Solution Approach 2:
Memory cells are designed with universal access capabilities that can handle both simple and complex operations through the same basic cell structure. The cells support multiple read/write operations per cycle through coordinated control of wordlines and bitlines, while maintaining the speed benefits of simplified single-operation access through optimized cell switching characteristics
Data Source
AI summary
A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.