Computational Memory Cell With Ratioless Write Port
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Solution Overview
Problem
Existing SRAM cells require a write ratio of 2 to 3 times the strength of the storage transistor for successful writing, leading to larger cell sizes and inefficiencies in computational operations.
Innovation Solution
A computational memory cell with a ratioless write port and isolation circuit, allowing write operations without needing to overcome the drive strength of the storage cell's PMOS transistor, and a second read port for enhanced functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stronger write transistors are used to overcome storage transistor drive strength, then write operation reliability is improved, but cell area increases
Solution Approach 1:
The write port is segmented into two independent write ports (first write port and second write port), each capable of performing write operations independently. This segmentation allows the write function to be distributed across multiple pathways, eliminating the need for oversized transistors in a single write port while maintaining reliable write capability.
Solution Approach 2:
The patent introduces intermediate control signals (first write control signal and second write control signal) that mediate between the write data and the storage cell. These control signals enable selective activation of different write ports and facilitate write operations without requiring the write transistors to continuously overcome the storage transistor drive strength, thus reducing the required transistor size.
2Ease of manufacture
If write transistor strength is increased to achieve ratioless writing, then manufacturing complexity is reduced, but cell area increases
Solution Approach 1:
The write control mechanism is made dynamic through the use of control signals that can selectively enable or disable different write ports based on operational requirements. This dynamic control allows the system to achieve ratioless writing (where write transistor strength does not need to significantly exceed storage transistor strength) by activating appropriate write paths, thereby simplifying manufacturing constraints without requiring larger cell area.
3Device complexity
If a single read port is used, then cell structure is simpler, but computational functionality is limited
Solution Approach 1:
The memory cell is designed with dual functionality where the same cell structure supports both memory storage and computational operations. The first and second read ports enable the cell to perform both read operations and computational operations (such as AND, OR, NAND, NOR, XOR, XNOR) using the stored data, thus achieving multi-functionality without significantly increasing structural complexity.
Solution Approach 2:
The patent implements partial read functionality where the first read port can perform both read and computational operations, while the second read port provides additional computational capability. This partial implementation of multiple read functions allows the cell to achieve enhanced computational versatility without fully duplicating the read port structure, thus balancing complexity and functionality.
Data Source
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AI summary
A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.