Computational Memory With Row ALU And Shared Cache
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Deep learning and neural network computations require significant power due to data movement between memory and processing elements, leading to inefficiencies such as increased complexity, processing time, and larger chip area requirements.
Innovation Solution
A computing device with an array of processing elements connected for SIMD operations, each with memory cells and cache for data storage and caching, where adjacent processing elements share caches to optimize data communication and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data is moved between memory and processing elements in traditional architectures, then computations can be performed, but power consumption increases significantly
Solution Approach 1:
The patent merges memory cells directly with processing elements into integrated computational units. Each processing element contains local memory cells that store data, eliminating the need for separate memory modules and reducing data movement distance. This integration allows computations to be performed in-place without charging and discharging capacitance of long wiring between independent memory and processing components.
Solution Approach 2:
The patent segments the computational system into multiple processing elements arranged in arrays, where each element handles specific computations locally. This segmentation allows data to be distributed across multiple local memory cells rather than being集中 in a single memory module, reducing the overall data movement required and enabling parallel processing with minimal inter-element communication.
2Productivity
If more memory and processing elements are added to handle deep learning computations, then computational capability increases, but chip area requirements increase
Solution Approach 1:
The patent implements a nested structure where memory cells are integrated within processing elements, which are arranged in arrays. Each processing element contains its own memory cells, creating a hierarchical nesting that maximizes functional density. This nested organization allows multiple computational units to share common wiring infrastructure and control logic, reducing the overall chip area required compared to traditional architectures with separate memory and processing blocks.
3Quantity of substance
If data is stored in separate memory modules, then memory capacity increases, but the complexity of data movement and access increases
Solution Approach 1:
The patent makes memory cells multi-functional by enabling them to serve both as storage elements and as computational elements. Each memory cell can store data and also participate in arithmetic operations through its integration with the processing element. This universality eliminates the need for separate memory access pathways and computation pathways, simplifying the overall data flow and reducing the complexity of data movement control logic.
Data Source
AI summary
A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.