Computational Memory Using Ternary Content Addressable Array
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Solution Overview
Problem
Conventional computer designs face challenges in increasing computational power while minimizing die area and cost, as adding memory close to the processing element increases overhead, and existing methods for improving processing speed in small memories are inefficient due to high bitwise operation overhead and sequential operand processing.
Innovation Solution
A computational memory device utilizing a ternary content addressable memory (TCAM) array with search lines and match lines, allowing for concurrent bitwise logical operations across multiple columns without the need for a physical arithmetic logic unit (ALU), enabling distributed processing and complex operations within the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a physical ALU is positioned close to memory to improve data bandwidth, then processing speed improves, but die area increases
Solution Approach 1:
The patent merges the ALU functionality directly into the memory array structure by using content-addressable memory cells that can perform bitwise logical operations. This integration eliminates the need for a separate physical ALU while maintaining high processing speed through concurrent operations within the memory array itself.
Solution Approach 2:
The memory array is designed to serve multiple functions: it can perform standard read operations, bitwise logical operations (AND, OR, XOR, NAND, NOR, XNOR), and content-addressable search operations. This multi-functionality eliminates the need for separate dedicated ALU circuitry, resolving the area-speed tradeoff.
2Productivity
If a one-bit SIMD processor is placed within memory circuitry to improve computational speed, then processing capability improves, but overhead increases and operands must be read sequentially
Solution Approach 1:
The memory array performs computational operations on its own stored data without requiring external sequential operand reading. The content-addressable nature of the memory allows parallel operation across multiple columns simultaneously, eliminating the sequential reading bottleneck and reducing overhead associated with external ALU processing.
3Productivity
If memory capacity is increased next to the ALU to improve data bandwidth, then processing performance improves, but die area and cost increase
Solution Approach 1:
The patent combines the ALU functionality with the memory array, creating a unified structure where computational operations occur within the memory itself. This eliminates the need for separate large-capacity memory blocks positioned adjacent to a dedicated ALU, thereby maintaining high data bandwidth while reducing overall die area.
Data Source
AI summary
A content-addressable memory (CAM) with computational capability is described. The CAM includes an array of CAM cells arranged in rows and columns with a pair of search lines associated with each column of the array and a match line associated with each row of the array. The array of CAM cells is configured to implement, for a given cycle, either a read operation of data contained in a single selected column, or one of a plurality of different bitwise logical operations on data contained in multiple selected columns. All of the pairs of search lines in the columns of the array are configured to a certain state to implement the read operation or one of the plurality of different bitwise logical operations. A result of the read operation or one of the plurality of different bitwise logical operations is outputted onto all of the match lines in the array.