Computational Memory With Write-Triggered In-Memory Updates
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Solution Overview
Problem
Existing computational memory systems face inefficiencies due to latency, resource underutilization, and complexity in managing queue-based work requests, leading to suboptimal performance and inflexibility, especially in data-intensive and heterogeneous computing environments.
Innovation Solution
A computational memory architecture that enables direct computation within memory modules in response to data writes, eliminating the need for queue-based models by automatically updating computed values in designated regions, utilizing validity bits and minimum recalculation periods to ensure result integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If queue-based work requests are used to manage computations in memory systems, then computational tasks can be coordinated, but latency increases and system complexity grows
Solution Approach 1:
The patent extracts the computational functionality from the traditional CPU-centric architecture and embeds it directly within the memory subsystem. Memory modules now contain integrated computing units that can execute computations locally without requiring coordination through complex queue-based mechanisms, thereby eliminating the source of latency while preserving computational capability.
Solution Approach 2:
The patent merges storage and computation functions into a unified memory module architecture. By combining memory cells with computational units, the system eliminates the need for separate CPU-memory communication queues, allowing computations to occur directly where data resides, thus reducing latency and simplifying task coordination.
2Ease of operation
If queue-based work requests are used to manage computations, then task coordination is possible, but device complexity increases
Solution Approach 1:
The patent removes the complex software management layer by extracting computational capability from the CPU and embedding it in memory. This eliminates the need for complex queue-based coordination software, reducing device complexity while maintaining ease of operation through simpler memory-access-driven computation triggering.
Solution Approach 2:
Memory modules with integrated computing units autonomously execute computations when triggered by data writes, without requiring external software coordination. This self-service capability eliminates complex queue management and reduces overall system complexity while maintaining operational ease.
3Power
If computations are performed remotely from data storage, then centralized processing is achieved, but data transfer bottlenecks increase
Solution Approach 1:
Instead of centralizing computation at a remote CPU and transferring data to it, the patent inverts the approach by embedding computation directly at the data storage location. This reverses the traditional data flow pattern, allowing computations to occur where data resides and eliminating data transfer bottlenecks while maintaining processing capability.
Solution Approach 2:
The patent applies local quality by embedding computational units directly within memory modules, enabling computations to occur locally where data is stored. This eliminates the need for data transfer to remote processors, improving data transfer efficiency while maintaining centralized processing capability through distributed computation nodes.
4Device complexity
If traditional memory architecture is used, then simple data storage is achieved, but computational capabilities are limited
Solution Approach 1:
The patent implements multi-functionality by designing memory modules that can both store data and execute computations. This universal architecture allows the same hardware component to perform multiple functions (storage and processing), enhancing adaptability and versatility while maintaining relative architectural simplicity compared to separate CPU-memory systems.
Solution Approach 2:
The patent combines storage and computation functions into unified memory modules, enabling these modules to perform both data retention and processing operations. This merging enhances computational capability while maintaining a relatively simple architecture where a single component type handles multiple functions, avoiding the complexity of fully distributed systems.
Data Source
AI summary
The disclosed memory architecture eliminates the need for the conventional queue-based work request model by allowing direct computation within memory modules in response to data writes. The system is designed to automatically update computed values, such as hashes, within a designated computational memory region in response to a write to a corresponding data set region, without explicit instructions from the host. The computation happens according to a defined policy, which may include computing a new result immediately after a write to a dataset segment, computing the result if no writes are detected to a dataset segment within a specified period of time, computing the result after a host reads an invalid compute validity bit, or the like.