Computational Memory Zero Disable for Low-Power Neural Dot Products
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Solution Overview
Problem
Deep learning neural networks require significant power consumption due to data movement between memory and processing elements, leading to inefficiencies such as increased complexity, processing time, and larger chip area requirements, particularly in battery-powered devices.
Innovation Solution
A processing device with an array of processing elements connected for direct communication, featuring an input zero detector and zero disable circuit to optimize data flow, and a controller that adds error-checking values to matrices for efficient parallel operations and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data is moved between memory and processing elements in conventional architectures, then computations can be performed, but power consumption increases significantly
Solution Approach 1:
The patent merges memory and processing elements into a unified computational memory structure where processing elements can directly access and compute with stored data without physical data movement. This integration eliminates the energy-consuming data transfer between separate memory and processing components while maintaining computational functionality.
Solution Approach 2:
The patent introduces an input zero detector as an intermediary component that monitors data before it enters the processing element. This detector identifies zero values and prevents unnecessary computational operations, thereby reducing power consumption without affecting the main computational flow.
2Reliability
If zero values are processed through full computational operations, then computational consistency is maintained, but power is wasted on unnecessary calculations
Solution Approach 1:
The patent applies preliminary action by detecting zero values in the input data before they reach the arithmetic logic unit. The input zero detector examines incoming data and activates the zero disable circuit in advance, preventing the ALU from performing unnecessary multiplication or addition operations on zero values, thus conserving energy while maintaining computational integrity.
Solution Approach 2:
The patent implements partial action by selectively disabling only those computational operations that would process zero values, rather than disabling all operations. The zero disable circuit partially inhibits the ALU operation only when justified by the presence of zero inputs, allowing full computational capability to remain available for non-zero data.
Data Source
AI summary
A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.