Computational Node Fusion in Reconfigurable Data Processors
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Solution Overview
Problem
In data processing systems with reconfigurable processors executing dataflow graphs, traditional pipelining methods require more resources and hamper overall throughput due to the inability to reuse resources across stages, leading to increased latency and reduced performance.
Innovation Solution
A method is disclosed where a compiler generates a pipeline of computational nodes interleaved with buffers, allowing for the comparison and removal of buffers based on latency, effectively fusing low-latency nodes to reduce the number of pipeline stages and optimize resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional pipelining methods are used with multiple buffers between computational stages, then resource isolation and stage independence are improved, but chip real-estate consumption increases and overall throughput decreases
Solution Approach 1:
The patent merges multiple computational nodes into fused node groups that share common buffers. Instead of having separate buffers for each computational stage, multiple nodes are combined to use shared buffer resources, reducing the total number of buffers required and freeing up chip real-estate while maintaining proper data flow isolation through the sharing mechanism.
Solution Approach 2:
Buffers are designed to serve multiple computational nodes simultaneously rather than being dedicated to single stages. The shared buffers can be accessed by multiple fused nodes according to data flow dependencies, making the buffer resources universal and multi-functional, thereby reducing overall resource consumption on the chip.
2Reliability
If traditional pipelining methods are used with multiple buffers between computational stages, then stage independence is improved, but system throughput and performance deteriorate
Solution Approach 1:
By fusing computational nodes into groups that share buffers, the patent reduces the number of pipeline stages and buffer access operations required. This merging eliminates redundant buffer management overhead and reduces latency in data transfer between stages, thereby improving overall system throughput while maintaining necessary isolation through controlled sharing.
Solution Approach 2:
The shared buffer architecture enables more continuous data flow between computational stages by reducing idle time associated with buffer management and stage synchronization. Fused nodes can更高效ly utilize the shared buffers, maintaining continuous useful action across pipeline stages rather than having interruptions from frequent buffer accesses.
3Productivity
If computational nodes are fused and buffers are removed based on latency comparison, then resource allocation efficiency is improved, but pipeline stage independence may be compromised
Solution Approach 1:
Computational nodes are fused into groups based on their latency characteristics and data flow dependencies. Nodes with compatible timing requirements are combined to share buffers, optimizing resource allocation efficiency. The fusion process maintains logical stage independence by preserving necessary synchronization points and data flow boundaries even though physical buffers are shared.
Solution Approach 2:
The patent applies different buffering strategies to different parts of the pipeline based on local requirements. Some nodes share buffers while others maintain independent buffers based on their specific latency needs and data flow characteristics. This localized approach to buffer allocation maintains stage independence where necessary while enabling resource sharing where appropriate.
Data Source
AI summary
A system includes an array of reconfigurable units further including a plurality of configurable elements such as pattern memory units (PMUs), pattern compute units (PCUs), and communication agents. The system further includes a configuration module to provide configuration data to configure the PMUs and PCUs. The systems further includes a compiler configured to generate a pipeline of a plurality of PCUs related to a dataflow graph, interleaved between a plurality of PMUs. Each PCU is coupled to perform calculations based on data received from a preceding PMU and store results of the calculations into a following PMU of the plurality of PMUs after a latency. The compiler is further configured to remove a PMU from the pipeline based on a comparison of the latencies of the PCUs. A corresponding method is also disclosed herein.