Computational Storage Buffer Transfer Between Compute Engines

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Solution Overview

Problem

Existing computational storage devices face challenges in optimizing the operation performance by efficiently managing computations across different computing namespaces and memory types, leading to suboptimal processing efficiency and resource utilization.

Innovation Solution

A computational storage device and method that involves a storage controller managing a nonvolatile memory, multiple accelerators in different computing namespaces, and a buffer memory to process computations sequentially, allowing for efficient data transfer and computation across these namespaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If intermediate computation results are stored in buffer memory for transfer between accelerators, then data transfer between computing namespaces is enabled, but buffer memory access time and complexity increase

Engineering Contradiction:

Improvedata transfer capabilityVSAvoidbuffer access time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges the buffer memory management functionality into the storage controller, which already exists in the system. The storage controller is enhanced to directly manage buffer memory allocations and transfers between accelerators, eliminating the need for separate buffer management mechanisms and reducing access overhead.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The storage controller acts as an intermediary between accelerators and buffer memory, centralizing the management of intermediate computation results. This mediator role allows for optimized data paths and reduced access complexity by providing a single point of control for buffer allocations and transfers.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple accelerators in different computing namespaces are used, then computational versatility is improved, but resource management complexity increases

Engineering Contradiction:

Improvecomputational versatilityVSAvoidresource management complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The storage controller is designed with multi-functional capabilities to manage multiple accelerators across different computing namespaces. It performs diverse functions including buffer memory allocation, data transfer coordination, and computation result management, thereby reducing the need for separate management mechanisms for each accelerator.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the management of computational resources by introducing computing namespaces that isolate and organize accelerators and their associated buffer memories. This segmentation allows independent management of each namespace while maintaining overall system coordination through the storage controller.

Inventive Principle:

Principle #1Segmentation

3Reliability

If fused execution commands are processed sequentially across multiple accelerators, then computational accuracy is improved, but processing speed decreases

Engineering Contradiction:

Improvecomputation accuracyVSAvoidprocessing speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The storage controller performs preliminary actions by pre-allocating buffer memory regions and preparing data transfer paths before fused execution commands are processed. This preliminary setup reduces the overhead during actual computation and enables more efficient sequential processing across accelerators.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuity of useful action by optimizing the data flow between accelerators through the storage controller. Intermediate results are continuously transferred and made available for subsequent computations without unnecessary idle time, maintaining a continuous processing pipeline that minimizes gaps between computational stages.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12561084B2Computational storage device configured to transfer intermediate data between compute engines and method for operating the device

Publication Date: 2026.02.24 SAMSUNG ELECTRONICS CO LTD

AI summary

A method for operating a computational storage device includes receiving, by a storage controller, a first computing namespace setting instruction from a first host device, receiving, by the storage controller, a second computing namespace setting instruction from a second host device, receiving, by the storage controller, a first program from the first host device, receiving, by the storage controller, a second program from the second host device, receiving, by the storage controller, a fused execution command processing, by a first accelerator, the first computation, storing, by the storage controller, a first computation result obtained by processing the first computation in a buffer memory, providing, by the storage controller, data stored in the buffer memory to a second accelerator different from the first accelerator and processing, by the second accelerator, the second computation on the data provided from the buffer memory.